Skhynix Inc.

Myeong-Woon Jeon

Jae-Yoon Lee

Hyung-Min Lee

A controller includes a processor suitable for reading target data based on a predetermined main read voltage, and on each of a plurality of candidate read voltages having different voltage values; a memory suitable for storing main coded data and candidate coded data which are obtained by reading the target data; an ECC suitable for decoding the main coded data to generate main decoded data, and decoding each of the candidate coded data to generate candidate decoded data; and a counter suitable for counting the number of error bits corresponding to the main decoded data, and counting each of numbers of error bits corresponding to each of the candidate decoded data; and a voltage setting circuit suitable for setting a candidate read voltage having a minimum number of error bits, among the candidate decoded data, and which is smaller than the number of error bits corresponding to the main decoded data, as the main read voltage.

Controller and operating method thereof

An operating method of a memory system includes: reading a first data from a particular data group among a plurality of data groups included in a memory device; performing a first error correction code (ECC) decoding for the first data; when the first ECC decoding fails, reading a plurality of the remaining data other than the first data from the particular data group; performing a second ECC decoding for the plurality of the remaining data; when the second ECC decoding fails, identifying data, to which the second ECC decoding fails, among the plurality of the remaining data; obtaining first and second soft read values respectively corresponding to the first data, to which the first ECC decoding fails, and the second data, to which the second ECC decoding fails; determining reliability of the first and second data based on the first and second soft read values; and correcting the first data based on the reliability of the first and second data.

Operating method of memory system

An operating method of a memory system includes: reading a first data from a particular data group among a plurality of data groups included in a memory device; performing a first error correction code (ECC) decoding for the first data; when the first ECC decoding fails, reading a plurality of the remaining data other than the first data from the particular data group; performing a second ECC decoding for the plurality of the remaining data; when the second ECC decoding fails, identifying data, to the second ECC decoding fails, among the plurality of the remaining data; obtaining first and second soft read values respectively corresponding to the first data, to which the first ECC decoding fails, and the second data, to which the second ECC decoding fails; determining reliability of the first and second data based on the first and second soft read values; and correcting the first data based on the reliability of the first and second data.

An operating method of a memory controller includes performing a soft read operation to read data stored in a semiconductor memory device using a soft read voltage, performing a soft decision ECC decoding operation to the read data based on a first log likelihood ratio (LLR) value, and performing the soft decision ECC decoding operation to the read data based on a second LLR value when the soft decision ECC decoding operation based on the first LLR value fails. The first and second LLR values are selected between a default LLR value and an updated LLR value. The updated LLR value is generated on a basis of numbers of error bits and non-error bits of the read data, which are obtained through the soft decision ECC decoding operation to the read data.

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Gyeonggi-do, South Korea

Myeong-Woon Jeon