Samsung Electronics Co., Ltd.

Myeong-O Kim

Min-Soo Kim

Sang-Uhn Cha

Kyo-Min Sohn

Jong-Cheol Lee

Sang-Joon Hwang

Tae-Yoon Lee

Seong-Jin Jang

Young-Sik Kim

Byung-Chul Kim

Reum Oh

Yun-sang Lee

Min-Sang Park

Sung-Min Seo

Jae-woong Lee

Won-Il Bae

Yong-Gyu Chu

Ho-Seok Seol

In-Woo Jun

Ki-Heung Kim

Hong-Jun Lee

Chi-Hwan Lee

Soo-hwan Kim

Jae-Won Ko

An error correction circuit of a semiconductor memory device including a memory cell array includes an error correction code (ECC) memory that stores an ECC and an ECC engine. The ECC is represented by a generation matrix. The ECC engine generates first parity data based on main data using the ECC, and corrects at least one error bit in the main data read from the memory cell array using the first parity data. The main data includes a plurality of data bits divided into a plurality of sub codeword groups. The ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub codeword groups. The column vectors have elements configured to restrict a location of a sub codeword group in which a mis-corrected bit occurs, in which the mis-corrected bit is generated due to error bits in the main data.

Semiconductor memory device error correction circuit, semiconductor memory device including the same, and memory system including the same

Semiconductor memory device may include a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The control logic circuit may, in a first write operation mode, control the I/O gating circuit to select a sub-page, read a first unit of data including a first sub unit of data, a second sub unit of data and a first parity data from the sub-page, and provide the first unit of data to the error correction circuit. The control logic circuit may also control the error correction circuit to perform an error-correcting code decoding on the first unit of data to generate syndrome data, generate second parity data based on a portion of the first unit of data and generate third parity data based on a write parity data, the second parity data and the syndrome data.

Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices

A memory device may include a pre-charge control circuit, an active control circuit, and a driver circuit. The pre-charge control circuit may be configured to receive an active command after receiving a pre-charge command for a first bank, determine whether or not a pre-charge operation for the first bank has ended when receiving the active command, and generate an active instruction signal according to a result of the determination. The active control circuit may be configured to generate an active control signal for an active operation according to the active instruction signal. The driver circuit may be configured to control an active operation according to the active control signal.

Memory device, and memory system including the same

Provided is a method of detecting a concentrated address of a semiconductor device using an n-bit address. The method includes dividing the n-bit address into k groups, wherein each of n and k is an integer equal to or greater than 2, for each group of the k groups, detecting one or more concentrated sub addresses corresponding to the group, and generating at least one concentrated address by combining the one or more concentrated sub addresses for the k groups.

Concentrated address detecting method of semiconductor device and concentrated address detecting circuit using the same

A bitline precharge voltage generator comprises a leakage trimming unit and a bitline precharge voltage providing unit. The leakage trimming unit applies a leakage current to an output node to place a bitline precharge voltage at an edge of a dead zone. The bitline precharge voltage providing unit provides the bitline precharge voltage to the output node, and sets the bitline precharge voltage to a target level. The bitline precharge voltage generator generates the bitline precharge voltage having a distribution including the dead zone.

Bitline precharge voltage generator, semiconductor memory device comprising same, and method of trimming bitline precharge voltage

A semiconductor memory device is provided. A memory cell array has a plurality of memory cells connected between a plurality of word lines and a plurality of bit-line pairs. A sense amplifier unit has a plurality of sense amplifiers connected with the bit-line pairs respectively and amplifies data of the bit-line pairs to a sensing voltage level. A command decoder decodes a command applied from the outside and outputs the decoded command. A plurality of input/output (I/O) gates electrically connects the bit-line pairs with corresponding I/O line pairs in response to a voltage level applied through a plurality of corresponding column selection lines. A column decoder decodes a column address and drives at least one of the column selection lines to a plurality of different voltages levels.

Semiconductor memory device

A method and semiconductor memory device for precharging a local input/output line. The semiconductor memory device, which may have an open bit line structure, transmits data through local input/output lines that are coupled to bit lines of first to n-th memory cell array blocks (n being a natural number). The semiconductor memory device may include a precharge unit configured to generate a plurality of precharge signals and a controller configured to control precharging of the at least one local input/output line responsive to block information corresponding to activation of at least one of the memory cell array blocks and responsive to at least one of the precharge signals.

Method of precharging local input/output line and semiconductor memory device using the method

A sense amplifier includes a reference signal providing unit and an internal sense amplification unit. The reference signal providing unit provides a reference bit line signal in response to a reference control signal. The internal sense amplification unit receives the reference bit line signal and data signals that correspond to the data. The received signals are provided through bit lines connected to the memory cell array. The internal sense amplification unit senses the received reference bit line signal and the data signals and amplifies the sensed signals. The sense amplifier senses data stored in memory cells connected to dummy bit lines of the outmost memory cell array of a semiconductor memory device such that the memory cells that are not used can be used. Accordingly, the design area and cost of the semiconductor memory device can be reduced.

Sense amplifier, semiconductor memory device including the same, and data sensing method

A semiconductor memory device including a bit line sense amplifier for amplifying a voltage corresponding to a charge stored in a capacitor of a memory cell and outputting an amplified voltage and an I/O sense amplifier for receiving the output of the bit line sense amplifier, amplifying a voltage level of the output and outputting an amplified voltage level is disclosed. The semiconductor memory device includes a sense amplification enable signal control portion which receives an initial sense amplification enable signal, sequentially delays the initial sense amplification enable signal by a plurality of predetermined time periods and selectively outputs a plurality of delayed sense amplification enable signals in view of both an operation speed and a manufacturing yield of a semiconductor memory device; a plurality of clocked sense amplifiers which each receive an output signal of the I/O sense amplifier, amplify the output signal of the I/O sense amplifier in response to each of the plurality of delayed sense amplification enable signals, and sequentially output an output signal of a power voltage level or a ground voltage level in response; and a previous-step output driving circuit which sequentially receives the output signals of the plurality of clocked sense amplifiers, delays the output signals of the plurality of clocked sense amplifiers by a predetermined time period, and then intercepts an output of the clocked sense amplifier of a previous step.

A sense amplifier circuit of a semiconductor memory device and a method of operating the same, in which the sense amplifier circuit includes a bit line sense amplifier connected with a bit line to sense and amplify a signal of the bit line, and a calibration circuit calibrating a voltage level of the bit line based on a logic threshold value of the bit line sense amplifier. The bit line sense amplifier senses and amplifies the signal of the bit line after the voltage level of the bit line is calibrated. The bit line sense amplifier may include a 2-stage cascade latch, which includes a first inverter having an input terminal connected with the bit line; and a second inverter which has an input terminal connected with an output terminal of the first inverter and an output terminal connected with the bit line and is enabled/disabled in response to a sensing control signal. The calibration circuit includes a switch element that is connected between the output terminal of the first inverter and the bit line and is turned on or off in response to a calibration control signal.

Sense amplifier circuit of semiconductor memory device and method of operating the same

A control unit for a semiconductor memory device, a semiconductor memory device and a method for controlling the same. The control unit of a semiconductor memory device includes control signal circuits, each control signal circuit to receive a master signal and to generate at least one of a plurality of control signals in response to the master signal, each of the plurality of core control signals to be generated after a delay specific to the core control signals after a transition of the master signal, the plurality of control signals to control the semiconductor memory device.

Semiconductor memory device and method for controlling the same

A frequency detection circuit and method of detecting the frequency of a clock signal, and a latency signal generation circuit for a semiconductor memory device that includes the frequency detection circuit. The frequency detection circuit includes a frequency detector and an output controller, which determines whether or not the frequency of the clock signal is higher than a predetermined value. Embodiments of the invention have an increased accuracy, increased efficiency, and a reduced current consumption over conventional art.

Circuit and method for detecting frequency of clock signal and latency signal generation circuit of semiconductor memory device with the circuit

The present invention discloses a semiconductor memory device that includes first and second memory banks. A first control signal generating circuit generates a first control signal responsive to an external clock. A first data output circuit transmits a first output data responsive to the first control signal. An internal clock signal generating circuit outputs first and second buffered clock signals responsive to the external clock. A second control signal generating circuit generates a second control signal responsive to the first buffered clock signal and the first control signal. A second data output circuit transmits a second output data responsive to the second control signal. A third data output circuit transmits a third output data responsive to the first and second buffered clock signals. The present invention prevents data read errors resulting from variations in power supply voltage and temperature.

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Suwon-si, South Korea

Myeong-O Kim