Skhynix Inc.

Osong Medical Innovation Foundation, Korea University Research and Business Foundation

Myeong Jae Park

Ji Hwan Park

Byung Kuk Yoon

Jun Il Moon

Kyung Hoon Kim

Woo Yeol Shin

Han Kyu Chi

Chang Kwon Lee

Su Hyun Oh

Jinhyung Lee

Jong Sun Park

Young Jun Park

Young Jun Ku

Kyu Young Kim

Jeong Kyoum Kim

Seong Yoon Kang

Seok Woo Choi

Disclosed are a bus inversion encoder module that utilizes future data in a data bus including a serializer with minimum latency and high transition reduction efficiency by comparing current data with both past data and the future data and encoding the current data, and a bus inversion system including the same. The bus inversion encoder module uses current data, past data, and future data transmitted through a bus and each including a plurality of bits, determines whether to invert the current data, and generates a current flag and coded current data by using whether to invert, an output flag, and the current data. The output flag is generated by summing the current flag and the coded current data and serially converting the current flag and the coded current data.

Bus inversion encoder module and bus inversion system including the same

A semiconductor device comprising: a first or a second path configured to transmit a first signal which swings between a ground level and a first level, a third path configured to transmit a second signal which swings between the ground level and a second level lower than the first level, a transmitter configured to output received the first signal through the first or second path as the second signal to the third path, and initialize in response to an enable signal, and a receiver configured to output received the second signal through the third path as the first signal through the first or second path, determine level of the second signal through a reference level that is regulated according to a fed-back level of an output terminal thereof, and initialize in response to the enable signal.

Semiconductor device including internal transmission path and stacked semiconductor device using the same

In an embodiment of the present disclosure, an integrated circuit includes: a first interface suitable for receiving first to Ndata, where N is an even number equal to or greater than 2, and first to Nmulti-phase clocks; an interface conversion circuit suitable for generating serial data based on the first to Ndata that are received through the first interface, and generating a data strobe signal for strobing the serial data based on the first to Nmulti-phase clocks that are received through the first interface; and a second interface suitable for receiving the serial data and the data strobe signal.

Integrated circuit and memory system

A semiconductor device comprises: a first or a second path configured to transmit a first signal which swings between a ground level and a first level, a third path configured to transmit a second signal which swings between the ground level and a second level lower than the first level, a transmitter configured to output received the first signal through the first or second path as the second signal to the third path, and initialize in response to an enable signal, and a receiver configured to output received the second signal through the third path as the first signal through the first or second path, determine level of the second signal through a reference level that is regulated according to a fed-back level of an output terminal thereof, and initialize in response to the enable signal.

A memory device includes a plurality of data input pads and at least one test data input pad. The memory device also includes a plurality of data input circuits corresponding to a plurality of channels, respectively, the plurality of data input circuits suitable for transmitting respective data received through the data input pads to the corresponding channels. The memory device further includes a test control circuit suitable for selecting at least one data input circuit among the plurality of data input circuits based on test mode information and suitable for controlling the selected data input circuit to transmit set data to the corresponding channel, during a test operation.

Data input circuit and memory device including the same

A clock generator circuit includes: first to Nnodes, where N is an even number equal to or greater than 2; and a parallel-to-serial conversion circuit suitable for parallel-to-serial converting signals of the first to Nnodes to output a clock through an output node, wherein, in an activation section of the clock, the signals of even-numbered nodes among the first to Nnodes have a first level, and the signals of odd-numbered nodes among the first to Nnodes have a second level which is different from the first level, and wherein, in a deactivation section of the clock, the signals of the first to Nnodes have the same level.

Clock generator circuit and integrated circuit including the same

A delay circuit includes a first delay line suitable for delaying a first clock by a delay value that is adjusted based on a delay control code; a delay control circuit suitable for comparing a phase of the first clock delayed through the first delay line with a phase of a second clock to generate the delay control code; and a second delay line having, based on a delay control code, a delay value corresponding to a half of the delay value of the first delay line.

Delay circuit and phase interpolator

A clock generation circuit may include a first clock generator and a second clock generator. The first clock generator may generate a first output clock toggling in synchronization with a rising edge of a first input clock. The second clock generator may generate a second output clock based on a second input clock and the first output clock. The second output clock may have a level changing based on the first output clock, and may be generated at a rising edge of the second input clock.

Clock generation circuit, and semiconductor device and system using the same

A semiconductor apparatus includes a pattern conversion circuit configured to generate conversion data in response to a monitoring enable signal, pattern select signals and parallel input data; a transmission circuit configured to output the conversion data as serial data in response to a plurality of clocks; a reception circuit configured to output the serial data as parallel output data in synchronization with the plurality of clocks; and a monitoring circuit configured to generate a result signal in response to the plurality of clocks, clock select signals and the serial data.

Semiconductor apparatus

A semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a period signal, the period signals periodically toggled in response to the command, output the data in response to the period signal, and discharge the charges of an internal node if the period signal is not toggled during a predetermined section.

Periodic signal generation circuit and semiconductor system including the same

A clock generation circuit may include a first clock generator, a second clock generator, and a common mode generator. The first clock generator may generate a multi-phase clock signal from a first clock signal. The second clock generator may generate a multi-phase clock signal from a second clock signal. The common mode generator may generate a reference voltage based on the first and second clock signals.

Clock generating circuit and semiconductor apparatus including the same

A phase detection circuit includes a sampling signal generation circuit configured to generate a plurality of sampling signals in response to a plurality of phase change clocks having different phases and data; a charging voltage generation circuit configured to compare the plurality of sampling signals, and change a voltage level of one charging voltage between a first charging voltage and a second charging voltage; and a comparison circuit configured to compare voltage levels of the first and second charging voltages, and generate a result signal.

Phase detection circuit

A semiconductor system may include a first semiconductor device configured to output a command and receive data. The semiconductor system may include a second semiconductor device configured to generate a periodic signal, the periodic signals periodically toggled in response to the command, output the data in response to the periodic signal, and discharge the charges of an internal node if the periodic signal is not toggled during a predetermined section.

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Icheon-si, South Korea

Myeong Jae Park