Electronics and Telecommunications Research Institute

Myeong Hoon Oh

Seong Woon Kim

Young Woo Kim

Sung Nam Kim

Dae Won Kim

Hag Young Kim

Jung Hyun Cho

Soo Cheol Oh

Sun Wook Kim

Jong Bae Moon

Chi Hoon Shin

Myung Joon Kim

Han Namgoong

Disclosed is a virtual desktop service method. The virtual desktop service method includes configuring and measuring users and resources according to predetermined criteria, copying operating system files and data files to be provided to the users before use request, receiving request to use a virtual machine from any one of the users and performing user authentication and work approval, and providing an operating system file and a data file of the any one of the users, among the copied operating system files and data files, to the any one of the users according to the use request to transmit a virtual desktop environment. Consequently, the virtual desktop service method performs a service to provide a virtual machine to a user in real time.

Virtual desktop service apparatus and method

Provided is a virtual desktop service, and disclosed is a system for providing a server virtual machine, including: a client configured to receive allocation of a virtual machine for using a virtual desktop service; a connection broker configured to control a type of virtual machine to be allocated to be classified according to user terminal registration information of the client, any one operation server to be selected among a plurality of operation servers, and the virtual machine to be allocated; the plurality of operation servers configured to provide the client with a virtual machine under a control of the connection broker; and a shared storage configured to store data related to the client for providing the virtual machine, and provide the stored data to the operation servers, a method of providing a server virtual machine, and a server device supporting the same.

Method and system for providing server virtual machine for real-time virtual desktop service, and server device supporting the same

Provided are a data transmission apparatus and method for transmitting data in a Delay-Insensitive (DI) data transmission method supporting a handshake protocol. The data transmission apparatus includes a sender which outputs a binary-valued logic signal based on binary-valued logic, and an encoder which encodes the binary-valued logic signal input through input wires into a multi-valued logic signal based on multi-valued logic and transmits the encoded multi-valued logic signal to a decoder through output wires. Here, the encoder includes a mapping table which stores input variables including the number of input wires and the number of output wires smaller than the number of input wires and the multi-valued logic signal corresponding to the input variables, and encodes the binary-valued logic signal into the multi-valued logic signal with reference to the mapping table.

Data transmission apparatus and method for transmitting data in delay-insensitive data transmission method supporting handshake protocol

Disclosed are an asynchronous pipeline system, a stage, and a data transfer mechanism. The asynchronous pipeline system having a plurality of stages based on a 4-phase protocol, includes: a first stage among the plurality of stages; and a second stage among the plurality of stages connected next to the first stage, wherein the first stage transmits and the second receives bundled data and control data through an always bundled data channel and on-demand data through an on-demand data channel according to need of the second stage.

Asynchronous pipeline system, stage, and data transfer mechanism

The present invention relates to a system and an apparatus for synchronization between heterogeneous periodic clock domains, a synchronization failure detecting circuit, and a data receiving method. The synchronization system between heterogeneous periodic clock domains including a sender and a receiver operated according to heterogeneous periodic first clock and second clock, respectively, includes: a sender that outputs a prediction clock obtained by delaying the first clock for a first time; and a receiver that predicts success and failure of synchronization between the first clock and the second clock by using the prediction clock and selectively delays the second clock for a second time according to the predicted results to synchronize the second clock with the first clock.

System and apparatus for synchronization between heterogeneous periodic clock domains, circuit for detecting synchronization failure and data receiving method

Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method.

Data transmitting device, data receiving device, data transmitting system, and data transmitting method

Provided are a microprocessor based on event-processing instruction set and an event-processing method using the same. The microprocessor includes an event register controlling an event according to an event-processing instruction set provided in an instruction set architecture (ISA) and an event controller transmitting externally generated events into the microprocessor. Therefore, the microprocessor may be useful to reduce its unnecessary power consumption by suspending the execution of its program when an instruction decoded to execute the program is an event-processing instruction, and also to cut off its unnecessary power consumption that is caused for an interrupt delay period since the program of the microprocessor may be executed again by immediately re-running the microprocessor with the operation of the event register and the event controller when external events are generated.

Growing community of inventors

Daejeon, South Korea

Myeong Hoon Oh