Samsung Electronics Co., Ltd.

Myeong-Dong Lee

Yoosang Hwang

Kiseok Lee

Hui-Jung Kim

Keunnam Kim

Junhyeok Ahn

Bong-Soo Kim

Chan-Sic Yoon

Yong Kwan Kim

Dongoh Kim

Jimin Choi

Changhyun Cho

Dongryul Lee

Minseong Choi

Jun-Hyeok Ahn

Jongmin Kim

Sunghee Han

Hyeon-Woo Jang

Sung-Hee Han

Sooho Shin

Hyo-Sub Kim

Minsu Choi

Yoo-Sang Hwang

Yoonyoung Choi

Eun-Jung Kim

Yong-kwan Kim

Chang-Hyun Cho

Ki-Seok Lee

Eunjung Kim

Seok H Lee

Jihun Lee

Wooyoung Choi

Ki Seok Lee

Sohyun Park

Seok Han Park

Augustin Jinwoo Hong

Jun-Won Lee

Yoo Sang Hwang

Jay-Bok Choi

Seokhan Park

Yongseok Ahn

Sung Hee Han

Inkyoung Heo

Jae Hyun Yoon

Min-Su Choi

Byoung-Wook Jang

Woojin Jeong

Hongjun Lee

Woosong Ahn

Ce-Ra Hong

Hye-Young Kang

Young-Sin Kim

Dong-Sik Kong

A semiconductor memory device may include a device isolation pattern in a substrate and defining a first active section of the substrate and a second active section of the substrate, a first bit line crossing the center of the first active section, a second bit line crossing a center of the second active section, a bit-line contact between the first bit line and a center of the first active section, and a storage node pad on an end of the second active section. The first and second active sections may be spaced apart from each other. The center of the first active section may be adjacent to the end of the second active section. A level of a bottom surface of the first bit line may be lower than a level of a bottom surface of the second bit line.

Semiconductor memory device having bit lines with different height

A semiconductor device includes a cell active pattern including a first portion and a second portion that are spaced apart from each other; a gate structure between the first portion and the second portion of the cell active pattern; a bit-line contact on the first portion of the cell active pattern; a connection pattern on the second portion of the cell active pattern; and a cell separation pattern in contact with the bit-line contact and the connection pattern, wherein the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact, an upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, and a lower portion of the second sidewall of the cell separation pattern is spaced apart from the bit-line contact.

Semiconductor device having a cell separation pattern in contact with the bit line contact

A semiconductor memory device includes: a device isolation pattern provided on a substrate to provide a first active portion and a second active portion; a first storage node pad disposed on the first active portion; a second storage node pad disposed on the second active portion; a pad separation pattern disposed between the first and second storage node pads; a word line disposed in the substrate to cross the first and second active portions; a bit line disposed on the pad separation pattern and crossing the word line; a buffer layer disposed on the pad separation pattern; and a mask polysilicon pattern interposed between the buffer layer and the bit line, wherein a side surface of the mask polysilicon pattern is substantially aligned to a side surface of the bit line, and the mask polysilicon pattern is vertically overlapped with the pad separation pattern.

Semiconductor memory device

A semiconductor memory device includes a device isolation pattern on a substrate and defining a first active section, a first storage node pad on the first active section, a word line in the substrate and extending across the first active section, a bit line on the first storage node pad and crossing over the word line, a storage node contact on one side of the bit line and adjacent to the first storage node pad, and an ohmic layer between the storage node contact and the first storage node pad. A bottom surface of the ohmic layer is rounded.

Semiconductor memory device and method of fabricating the same

Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

Method of fabricating semiconductor memory device having protruding contact portion

Semiconductor memory devices having protruding contact portions

A semiconductor memory device includes a substrate having a first active pattern including first and second source/drain regions, a gate electrode intersecting the first active pattern and disposed between the first and second source/drain regions, a bit line intersecting the first active pattern and electrically connected to the first source/drain region, a spacer disposed on a sidewall of the bit line, a contact electrically connected to the second source/drain region and spaced apart from the bit line with the spacer interposed therebetween, an interface layer disposed between the second source/drain region and the contact, and forming an ohmic contact between the second source/drain region and the contact, and a data storage element disposed on the contact. A bottom of the contact is lower than a top surface of the substrate. The contact is formed of a metal, a conductive metal nitride, and/or a combination thereof.

Semiconductor memory device and method for manufacturing the same

According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

Semiconductor devices and methods of fabricating the same

Disclosed is a semiconductor device comprising a substrate including a first region and a second region, a first gate pattern on the substrate of the first region, and a second gate pattern on the substrate of the second region. The first gate pattern comprises a first high-k dielectric pattern, a first N-type metal-containing pattern, and a first P-type metal-containing pattern that are sequentially stacked. The second gate pattern comprises a second high-k dielectric pattern and a second P-type metal-containing pattern that are sequentially stacked.

Semiconductor device

First and second mask layers are formed on a target layer. The second mask layer is patterned to form second mask patterns each of which having a rhomboid shape with a first diagonal length and a second diagonal length. A trimming process is performed on the second mask patterns to form second masks by etch. First portions of first opposite vertices of each second mask pattern are etched more than second portions of second opposite vertices of each second mask pattern. A first diagonal length between the first opposite vertices is greater than a second diagonal length between the second opposite vertices. The first mask layer is patterned to form first masks by etching the first mask layer using the second masks as an etching mask. The target layer is patterned to form target patterns by etching the target layer using the first masks as an etching mask.

Method of forming a pattern and method of manufacturing a semiconductor device using the same

An integrated circuit (IC) device including a line structure including a conductive line formed on a substrate and a lower insulation capping pattern; an insulation spacer covering a sidewall of the line structure; a conductive plug spaced apart from the conductive line in a first horizontal direction; a lower insulation fence spaced apart from the conductive line in the first horizontal direction, the lower insulation fence having a sidewall that contacts the conductive plug; and an upper insulation fence including a first portion covering the lower insulation capping pattern and a second portion covering the lower insulation fence, wherein a width of the second portion in a second horizontal direction perpendicular to the first horizontal direction is different from a width of the lower insulation fence in the second horizontal direction.

Integrated circuit (IC) device

An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

Integrated circuit devices

A semiconductor device includes a substrate having a trench, a bit line in the trench, a first spacer extending along the trench and at least a portion of a side surface of the bit line and in contact with the bit line, and a second spacer disposed within the trench on the first spacer. The bit line is narrower than the trench, and the first spacer includes silicon oxide. A method of forming a semiconductor device includes forming a trench in a substrate, forming a bit line within the first trench of width less than that of the first trench, and forming a first spacer that lines a portion of the trench and includes silicon oxide in contact with at least a portion of a side surface of the bit line, and forming a second spacer over the first spacer in the trench.

Semiconductor device and method for fabricating the same

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Seoul, South Korea

Myeong-Dong Lee