Samsung Electronics Co., Ltd.

Myeon-Koo Kang

Yong-Kyu Jang

Young-Kuil Joo

Young-pil Kim

Hyung-Moo Park

In-kyun Jun

Young-Pil Kim

Young-woo Seo

Won-shik Lee

Jih-Oh Kwag

Jong-Eup Shin

The present invention provide a reflective-transmission type TFT LCD wherein each of the reflective pixel electrode and the transmissive pixel electrode is connected directly to a source electrode of a thin film transistor, or the transmissive pixel electrode are concurrently formed with gate electrode and made with double layer of transparent conduction layer and metal layer which can be used as parameter conduction layer between the transparent conduction layer and the reflective pixel electrode. According to one aspect of the present invention, the reflective transmission type thin film transistor liquid crystal display (TFT LCD) comprises a glass substrate, at least one thin film transistor on the substrate for controlling a pixel, passivation layer having at least one contact hole in a source region of the thin film transistor, a transmissive pixel electrode which is formed on the passivation layer and is connected with a source electrode of the source region through a contact hole, a reflective pixel electrode which is formed on the passivation layer and is connected with the source electrode of the source region through a contact hole. And the pixel area is composed of a transparent area in which only the transmissive pixel electrode of whole pixel electrode exist and a reflective area in which the reflective pixel electrode exist.

Reflective-transmission type thin film transistor liquid crystal display with non-oxidizing metal layer in first pixel electrode

The present invention provide a reflective transmission type TFT LCD wherein each of the reflective pixel electrode and the transmissive pixel electrode is connected directly to a source electrode of a thin film transistor, or the transmissive pixel electrode are concurrently formed with gate electrode and made with double layer of transparent conduction layer and metal layer which can be used as parameter conduction layer between the transparent conduction layer and the reflective pixel electrode.

Reflective-transmission type thin film transistor liquid crystal display

Disclosed is a reflection type liquid crystal display and a method for fabricating the same. The reflection type liquid crystal display comprises a reflection electrode of which surface has a plurality of irregular and convex polygons, widths of respective ravines between the convex polygons being constant. Thus, since sizes and heights of the convex polygons are irregular in all directions and flat regions corresponding to the ravines are highly decreased, light reflectivity is enhanced and misalignment of liquid crystal molecules is minimized.

Reflection type liquid crystal display and a method for fabricating the same

A reflection type liquid crystal display device having a reflection electrode with an enhanced reflectivity and a method for fabricating the same includes a dimple on a convex of the reflection electrode. The method for fabricating such a reflection type liquid crystal display uses a photo-sensitive organic insulation film to form bumps for the convex-concave structure, thus increases only the number of times of exposures, thereby simplifying the overall process.

Method for fabricating a reflection type liquid crystal display

The operating speed and refresh characteristics of an embedded memory logic device having a silicide layer is improved by excluding the silicide from the source/drain region between access gates and pass gates in a cell array region, thereby reducing leakage current. The source/drain region between access gates and pass gates are also lightly doped to further reduce leakage current. An embedded memory logic device fabricated in accordance with the present invention includes a semiconductor substrate including first and second regions. A first gate electrode is formed over the first region. A first drain region doped with a first impurity is formed in the semiconductor substrate on one side of the first gate electrode, and a first source doped with a second impurity is formed in the semiconductor substrate on the other side of the first gate electrode. A second gate electrode is formed on a second region of the semiconductor substrate, and second source/drain regions doped with a third impurity are formed in the semiconductor substrate on both sides of the second gate electrode. Also, a third gate electrode is formed on the second region of the semiconductor substrate, and third source/drain regions doped with a fourth impurity are formed on both sides of the third gate electrode. Metal silicide layers are formed on the first through third gate electrodes, on the first drain region, and on the second and third source/drain regions.

Embedded memory logic device using self-aligned silicide and manufacturing method therefor

Embedded memory logic device using self-aligned silicide and

Methods of forming integrated circuits having memory cell arrays therein and peripheral circuits therein include the steps of selectively forming more lightly doped source and drain regions for transistors in the memory cell arrays. These more lightly doped source and drain regions are designed to have fewer crystalline defects therein caused by ion implantation, so that storage capacitors coupled thereto have improved refresh characteristics. Preferred methods include the steps of forming a first well region of first conductivity type (e.g., P-type) in a memory cell portion of a semiconductor substrate and a second well region of first conductivity type in a peripheral circuit portion of the semiconductor substrate extending adjacent the memory cell portion. First and second insulated gate electrodes are then formed on the first and second well regions, respectively, using conventional techniques. First dopants of second conductivity type are then implanted at a first dose level into the first and second well regions, using the first and second insulated gate electrodes as an implant mask. These dopants are then diffused to form lightly doped source and drain regions adjacent the first and second insulated gate electrodes. Second dopants of second conductivity type are then selectively implanted at a second dose level, greater than the first dose level, into the second well region using self-alignment techniques. However, these dopants are preferably not implanted into the first well region. These second dopants are then diffused into the second source/drain regions.

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Seoul, South Korea

Myeon-Koo Kang