Kabushiki Kaisha Toshiba

Other

Mutsuo Morikado

Jeffrey P Gambino

Jack Allan Mandelman

Fumitaka Arai

Herbert Lei Ho

Hiroaki Tsunoda

Kiyomi Naruke

Tomoki Higashi

Naoyuki Shigyo

Takeshi Shimane

Tohru Maruyama

According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: first device regions divided by first isolation films and second device regions divided by second isolation films a gate insulating film formed on the semiconductor substrate; a first element including: a first gate formed on the gate insulating film in the first device regions, a first inter-electrode insulating film formed on the first gate and on the first isolation films, and a second gate formed on the first inter-electrode insulating film; and a second element including: a third gate formed on the gate insulating film in the second device regions, and a fourth gate formed on the third gate and on the second isolation films; wherein a thickness of the third gate is larger than a thickness of the first gate.

Semiconductor memory device and method for manufacturing the same

According to one embodiment, a semiconductor memory device includes each of memory cells including a floating electrode above a semiconductor substrate via the gate insulator, a control gate electrode above the floating gate electrode via a first inter-gate insulator, first diffusion layers as source or drain, a contact electrode portion including a bottom electrode with an opening and a top electrode on the bottom electrode, the bottom electrode being arranged on the first gate insulator having the opening, the top electrode being electrically connected to the semiconductor substrate via the first opening, and a connection diffusion layer formed in the semiconductor substrate below the first opening.

Nonvolatile semiconductor memory device and method of fabricating the same

According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cells without a source region and a drain region, and a first insulating film. The memory cells are arranged adjacent to one another on the semiconductor substrate and include a first gate electrode including a charge accumulation layer. A current path functioning as a source region or a drain region of a selected memory cell is formed in the semiconductor substrate when a voltage is applied to the first gate electrode of one of unselected memory cells. The first insulating film is formed on the semiconductor substrate to fill a region between the first gate electrodes of the memory cells adjacent to each other.

Semiconductor memory device including charge accumulation layer

A nonvolatile semiconductor device and method having a plurality of series-connected memory cells with floating and control gate electrodes, and a first insulating layer formed between the gate electrodes. One of the memory cells has the floating gate formed to contact the control gate electrode through an aperture in the insulating layer. The insulating layer is removed to form spaces between the gate electrodes. A second insulating film is formed in the spaces between the gate electrodes. The dummy electrode supports the series of gate electrodes to maintain the spaces between the electrodes. The second insulating layer is formed to be continuous in the spaces and on side surfaces of the gate electrodes. The second insulating layer may have a stacked structure with n layers in the spaces and (n&#x2212;1)/2 layers on the side surfaces.

Semiconductor nonvolatile memory device with inter-gate insulating film formed on the side surface of a memory cell and method for manufacturing the same

A nonvolatile semiconductor memory device according to one embodiment includes: a memory cell array; word lines each connected to nonvolatile memory cells; and a control circuit. When executing the data reading operation, the control circuit applies to a selected word line connected to a selected memory cell a first voltage obtained by adding a first adjusting voltage to an intermediate voltage between adjoining two of the threshold voltage distributions; applies to first non-selected word lines adjoining the selected word line a second voltage obtained by subtracting a second adjusting voltage from a reading pass voltage; applies to second non-selected word lines adjoining the first non-selected word lines a third voltage obtained by adding the second adjusting voltage to the reading pass voltage; and applies to third non-selected word lines, the third non-selected word lines being non-selected word lines except the first and second non-selected word lines, the reading pass voltage.

Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory includes a memory cell string having a plurality of memory cell transistors connected in series, a selection gate transistor connected in series with one end of the memory cell string, and having a gate electrode provided on a gate insulating film on a semiconductor substrate, and an element isolation insulating layer which is provided in the semiconductor substrate. The gate electrode includes a first gate electrode provided on the gate insulating film, a first and second insulating films provided on the first gate electrode, and a second gate electrode provided on the second insulating film and the element isolation insulating layer, and electrically connected to the first gate electrode. An first upper surface portion of the element isolation insulating layer below the second gate electrode is leveled with an upper surface of the first gate electrode.

Nonvolatile semiconductor memory and manufacturing method thereof

A non-volatile memory of a semiconductor device has a tunnel insulation film provided on the active area; a floating gate electrode provided on the tunnel insulation film; a control gate electrode provided over the floating gate electrode; and an inter-electrode insulation film provided between the floating gate electrode and the control gate electrode, wherein, in a section of the non-volatile memory cell in a channel width direction, a dimension of a top face of the active area in the channel width direction is equal to or less than a dimension of a top face of the tunnel insulation film in the channel width direction, and the dimension of the top face of the tunnel insulation film in the channel width direction is less than a dimension of a bottom face of the floating gate electrode in the channel width direction.

Semiconductor device and method for manufacturing the same

According to one embodiment, a non-volatile semiconductor storage device includes a control circuit. When performing a read operation, the control circuit is configured to: apply a first voltage to a selected word line that is connected to a selected memory cell, the first voltage being a voltage between a plurality of threshold voltage distributions; apply a second voltage to a first unselected word line adjacent to the selected word line, the second voltage being not more than the first voltage; apply a third voltage to a second unselected word line adjacent to the first unselected word line, the third voltage being not less than a read pass voltage at which non-volatile memory cells become conductive; and apply the read pass voltage to a third unselected word line, the third unselected word line being an unselected word line other than the first unselected word line and the second unselected word line.

Non-volatile semiconductor storage device and method of controlling the same

NAND flash memory with selection transistor having two-layer inter-layer insulation film

A semiconductor memory in which each memory cell in a NAND flash memory includes a columnar floating gate formed on an element region with a gate insulating film interposed between the floating gate and the element region, diffusion layers formed at portions of the element region located below both sides of the floating gate, and a control gate formed so as to surround the floating gate with an IPD film interposed between the control gate and the floating gate, the IPD film formed on a side surface of the floating gate.

NAND flash memory and method of manufacturing the same

A semiconductor device comprises: a channel region of a transistor formed in a predetermined region of silicon layer formed on insulation film; a gate electrode formed on the channel region via gate insulation film; and source/drain regions formed in the silicon layer thicker than said channel region located out of the channel region, wherein the transistor is a memory element constituting the channel region as a floating body cell.

Semiconductor device and manufacturing method of the same

According to an aspect of the present invention, there is provided a semiconductor device including an insulated gate field effect transistor including a gate electrode film formed, via a gate insulating film, on a semiconductor film formed on a support substrate via an insulating film, and a source region and drain region formed in the semiconductor film to sandwich the gate electrode film in a gate length direction, a support substrate contact including a polysilicon film formed on a first opening via a silicon oxide film, the first opening extending through the semiconductor film and the insulating film and reaching the support substrate, an interlayer dielectric film formed on the semiconductor film and the support substrate contact, and an interconnection connected to the polysilicon film via a conductive material, the conductive material filling a second opening, which extends through the interlayer dielectric film and reaches the support substrate contact.

Semiconductor device and method of manufacturing the same

A semiconductor memory including a memory cell which is a MOSFET formed on an SOI substrate. The memory cell has a gate electrode connected to a word line, a drain region connected to a bit line, and a grounded source region. An operation of reading out data written in the memory cell is performed under a biasing condition by which a relationship Vd&#x3e;Vg&#x2212;Vthholds between a gate voltage Vg to be applied to said gate electrode, a drain voltage Vd to be applied to said drain region, a threshold voltage Vthof said MOSFET when a predetermined amount of holes are stored in a body region of the memory cell, and a threshold voltage Vthof said MOSFET when holes whose amount is smaller than the predetermined amount are stored in the body region.

Semiconductor memory and read method of the same

A semiconductor device includes second to fourth semiconductor layers, a gate electrode, and an insulating film. The second semiconductor layer is formed on a first semiconductor layer and has a projecting shape. The third and fourth semiconductor layers are formed on the first semiconductor layer to be in contact with the second semiconductor layer and oppose each other via the second semiconductor layer. The gate electrode is in contact with the second semiconductor layer with a gate insulating film interposed therebetween and forms a channel in the second semiconductor layer. The insulating film is formed in the first semiconductor layer located immediately under the third and fourth semiconductor layers.

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Yokohama, Japan

Mutsuo Morikado