Kioxia Corporation

Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Mutsumi Okajima

Takeshi Yamaguchi

Toshiharu Tanaka

Natsuki Fukuda

Atsushi Oga

Yasuaki Ootera

Tsuyoshi Kondo

Yoshihiro Ueda

Naoharu Shimomura

Tsutomu Nakanishi

Michael Arnaud Quinsat

Masaki Kado

Nobuyuki Umetsu

Hiroyuki Ode

Keiji Ikeda

Akihito Yamamoto

Nobuyoshi Saito

Takeshi Takagi

Masanori Komura

Takafumi Masuda

Susumu Hashimoto

Takayuki Tsukamoto

Tsuneo Inaba

Shiho Nakamura

Takayuki Ishikawa

Atsuhiro Sato

Hirofumi Inoue

Shinichiro Shiratake

Shinji Miyano

Kotaro Noda

Hidetoshi Saito

Masaharu Wada

Kiyomi Naruke

Hiroki Tokuhira

Daina Inoue

Jungo Inaba

Mamoru Ishizaka

Tsutomo Nakanishi

A magnetic memory includes first magnetic members extending along a first direction. First and second wirings are spaced apart from the first magnetic members on a second end side of the first magnetic members. At least one of the first magnetic members is between the first and second wirings in a plan view from the first direction. A second magnetic member has a first portion facing the first wiring and electrically connected to a first magnetic member on one side and a second portion facing the first wiring on an opposite side. The second portion is electrically connected to another first magnetic member. A control circuit causes a current to flow through one of the first wiring or the second wiring when data is written into the first magnetic member that is between the first wiring and the second wiring.

Magnetic memory

A semiconductor memory device includes: a memory cell array including memory cells, each including an oxide semiconductor transistor; a first insulating layer disposed above the memory cell array; a first wiring layer disposed between the memory cell array and the first insulating layer; a second insulating layer extending in a vertical direction. The second insulating layer has an annular cross-section. The semiconductor memory device includes a third insulating layer further disposed over the first insulating layer, a portion of the third insulating layer being surrounded by the second insulating layer.

Semiconductor memory device

A semiconductor memory device comprises: memory layers arranged in a first direction; and a first wiring extending in the first direction. The memory layers each comprise: a memory portion; a transistor; and a second wiring. The transistor comprises: a semiconductor layer electrically connected between the memory portion and the first wiring; a gate electrode facing the semiconductor layer and electrically connected to the second wiring; and a gate insulating film provided between the semiconductor layer and the gate electrode. The semiconductor layer faces surfaces of the gate electrode on one side and the other side in the first direction. In a cross section perpendicular to the first direction and including a part of the transistor corresponding to one of the memory layers, the first wiring comprises: a first surface in contact with the transistor; and a second surface not in contact with the transistor.

A semiconductor memory device comprises: memory layers arranged in a first direction; and a first and a second via wirings having different positions in a second direction. The memory layer comprises: a first transistor electrically connected to the first via wiring; a memory portion electrically connected to the first transistor; a wiring electrically connected to the first transistor; a second transistor electrically connected to the second via wiring; and an electrode provided in a current path between the second transistor and the wiring. The second transistor comprises: a semiconductor layer electrically connected to the electrode and the second via wiring; and a gate electrode facing the semiconductor layer. The semiconductor layer faces at least one of surfaces on one side or the other side in the first direction of the gate electrode. The electrode includes a portion arranged with the second via wiring in a third direction.

A memory device includes a first conductor and a charge storage film extending along a first direction; a first semiconductor of a first conductive type; a second and third semiconductor each of a second conductive type; and a stack comprising a second conductor, a first insulator, and a third conductor sequentially stacked along the first direction and each extending along a second direction. The first conductor, the charge storage film, the first semiconductor, and the stack are arranged in this order along a third direction. The second semiconductor is in contact with the first semiconductor and the second conductor, between the second conductor or the first insulator and the charge storage film.

Memory device

A semiconductor memory device includes a plurality of memory portions arranged in a first direction, a plurality of semiconductor layers arranged in the first direction and electrically connected to the plurality of memory portions respectively, a plurality of gate electrodes arranged in the first direction and opposed to the plurality of semiconductor layers respectively, a gate insulating film disposed between the plurality of semiconductor layers and the plurality of gate electrodes, a first wiring extending in the first direction and connected to the plurality of gate electrodes, and a plurality of second wirings arranged in the first direction and connected to the plurality of semiconductor layers respectively. The plurality of semiconductor layers are opposed to surfaces on one side and the other side of each of the plurality of gate electrodes in the first direction via the gate insulating film.

A storage device includes: a memory unit and a first pillar. The first pillar includes: a first region having a third portion between a first and a second portion respectively having a first and a second maximum diameter, and having a first minimum diameter, the first and second portions defining a first distance; a second region having a sixth portion between a fourth and a fifth portion respectively having a third and a fourth maximum diameter, and having a second minimum diameter, the fourth and fifth portions defining a second distance; and a third region between the first and second regions, having a ninth portion between a seventh and an eighth portion respectively having a fifth and a sixth maximum diameter, and having a third minimum diameter, the seventh and eighth portions defining a third distance shorter than each of the first and second distances.

Storage device and method for manufacturing storage device

According to one embodiment, a device includes: a circuit on a first surface of a substrate and including a first contact; an aluminum oxide layer above the substrate in a first direction perpendicular to the first surface; a cell including a capacitor provided in the aluminum oxide layer; a first conductive layer provided between the substrate and the aluminum oxide layer in the first direction and connected to the cell; a first insulating layer between the first conductive layer and the substrate in the first direction; a second insulating layer adjacent to the aluminum oxide layer in a second direction parallel to the first surface and provided above the substrate in the first direction; and a second contact in the second insulating layer and above the first contact in the first direction to connect the cell to the first contact.

Memory device and method for manufacturing the same

According to one embodiment, a memory device includes: a first chip including a first insulating layer and a first pad; a plurality of memory units provided in a first area of the first insulating layer and arranged at first intervals in a first direction parallel to a surface of the first chip; a plurality of mark portions provided in a second area of the first insulating layer and arranged at second intervals in the first direction; a second chip including a second pad connected to the first pad and overlapping the first chip in a second direction perpendicular to the surface of the first chip; and a circuit provided in the second chip.

Memory device having multiple chips and method for manufacturing the same

A semiconductor memory device includes: memory units arranged in a first direction; first semiconductor layers arranged in the first direction and electrically connected to the memory units; first gate electrodes arranged in the first direction and opposed to the first semiconductor layers; a first wiring extending in the first direction and connected to the first semiconductor layers; second wirings arranged in the first direction, and connected to the first gate electrodes; second semiconductor layers arranged in the first direction and disposed at first end portions of the second wirings; second gate electrodes arranged in the first direction and opposed to the second semiconductor layers; third semiconductor layers arranged in the first direction and disposed at second end portions of the second wirings; and third gate electrodes arranged in the first direction and opposed to the third semiconductor layers.

Semiconductor memory device with a plurality of memory units

A magnetic memory of the present embodiment includes an electrode extending along a plane including a first direction and a second direction, a first wiring extending in the first direction, second wirings between the electrode and the first wiring, extending in the second direction and arranged in the first direction, first magnetic members each including a first part electrically connected to the first wiring and a second part electrically connected to the electrode, extending in a third direction, and being positioned between neighboring two of the second wirings when seen from the third direction, and a control circuit. When writing first information to one first magnetic member, the control circuit supplies first current to at least two second wirings positioned on one side of the one first magnetic member in the first direction.

A magnetic memory of an embodiment includes: a first magnetic member including a first and second portions and extending in a first direction; a first and second wirings disposed to be apart from the first magnetic member and extending in a second direction intersecting the first direction, the first and the second wirings being separated from each other in a third direction intersecting the first and second directions, the first magnetic member being disposed to be apart from a region between the first wiring and the second wiring in the first direction; and a second magnetic member surrounding at least parts of the first and second wirings, the second magnetic member including a third portion located to be more distant from the first magnetic member, a fourth portion located to be closer to the first magnetic member, and a fifth portion located in the region.

A semiconductor memory device, includes: a first region including a first memory cell array; a second region arranged with the first region; and a third region arranged with the second region and including a second memory cell array. Each memory cell array includes: a field effect transistor above a semiconductor substrate, including a gate, a source, and a drain, the gate being connected to a first wiring, and one of the source and the drain being connected to a second wiring; and a capacitor below the transistor, including a first electrode connected to the other of the source and the drain, a second electrode facing the first electrode, and a third electrode connected to the second electrode and extending to the second region. The second region includes a conductor, the conductor connecting the third electrodes of the memory cell arrays.

A device includes a stack above a substrate in a first direction perpendicular to a surface of the substrate, the stack including conductive layers; a semiconductor layer neighboring the stack in a second direction parallel to the surface of the substrate; a memory layer between the first stack and the semiconductor layer; memory cells between the conductive layers and the semiconductor layer; a first transistor connected between one end of the semiconductor layer in a third direction parallel to the surface of the substrate and crossing the second direction and a first interconnect in the first direction; and a second transistor connected between the other end of the semiconductor layer and a second interconnect in the first direction.

Growing community of inventors

Mie, Japan

Mutsumi Okajima