Intel Corporation

Muthurajan Jayakumar

William S Wu

Stephen S Pawlowski

Peter D MacWilliams

Sunny C Huang

Bindi A Prasad

Vijay Kumar Goru

Mani Azimi

Dilip K Sampath

Daniel G Lau

Len J Schultz

Ronald L Mosgrove

Ravi Eakambaram

John W C Fu

Leonard J Schultz

Hugh Bynum

A bus agent defers an ordered transaction if the transaction cannot be completed in order. When an ordered transaction is deferred, its visibility for the next ordered transaction is asserted if it can guarantee a sequential order of the ordered transaction and the next ordered transaction. This visibility indication allows the bus agent to proceed with the next ordered transaction without waiting for the completion status of the deferred transaction. The visibility indication provides fast processing of ordered transactions.

Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system

An apparatus and method for controlling interrupts in a computer are disclosed, in which programmable software operates to control when data concerning the interrupt having highest priority is to be provided, and hardware logic operates to control how that data is provided. An interrupt vector register is included in the computer CPU. The interrupt vector register does not act like the typical register. It is not a physical register, and cannot be written to. A read to this register by the programmable software, triggers the hardware logic. Once triggered, this logic performs certain control tasks, the end result of which is returning to the programmable software, a vector corresponding to the interrupt having highest priority. The programmable software can implement various software policies, in addition to the hardware policy implemented by the hardware logic.

Apparatus and method for initiating hardware priority management by software controlled register access

A method and apparatus for handling cache snoop errors. According to one method disclosed, a snoop cycle having a snoop address is generated by a first bus agent. A second bus agent detects a snoop error in response to that bus cycle. As a result of the detected snoop error, the snoop error is signaled to the first bus agent, the bus agent which generated the snoop cycle.

Method and apparatus for detecting and compensating for certain snoop errors in a system with multiple agents having cache memories

A split transaction bus in a computer system that permits out-of-order replies in a pipelined manner using an additional bus for use in the response phase.

Method and apparatus for performing out-of-order bus operations in which an agent only arbitrates for use of a data bus to send data with a deferred reply

A method is provided for selecting a bootstrap processor from among the processors of a multiprocessor system. Each processor has an identity code and each processor that is eligible to serve as the bootstrap processor sends an election message to processors having lower valued identity codes. If no processor having a lower valued identity code responds to the election message, the processor that originated the election message designates itself as the bootstrap processor and sends a message to all processors indicating itself as the bootstrap processor.

Bootstrap processor selection architecture in SMP system

Methods and apparatus are disclosed for determining whether the highest priority pending interrupt is an active level-triggered interrupt. One method includes: determining whether the vector corresponding to the highest priority pending interrupt matches the vector associated with a particular interrupt input; if it does, determining whether that particular interrupt input is programmed to be a level-triggered interrupt; if it is, determining whether the level-status of that particular interrupt input is active; and, if it is, sending a level-triggered active message for the highest priority pending interrupt, by maintaining the set status of a particular bit. One embodiment of the present invention includes an interrupt service register operable to indicate when an interrupt is being serviced, an interrupt request register operable to indicate when an interrupt is pending, and a comparator operable to compare the vector corresponding to the highest priority pending interrupt with the vector associated with the particular interrupt input. Included also is a control generator coupled to the comparator, and operable to selectively clear and/or set bits contained in the interrupt service register and in the interrupt request register. The present invention supports both edge-triggered and level-triggered interrupts, without the need for a trigger mode register or other similar overhead house-keeping controls and related storage logic, and without any hand-shake requirements.

Method and apparatus for handling multiple level-triggered and

Method and apparatus for performing bus operations in a computer system

In a microprocessor system having a bus clock running at a bus clock rate, a method for reducing an idle interval between a first data transfer and a second data transfer, the method comprising the steps of:

Mechanism for data strobe pre-driving during master changeover on a

Mechanism for efficiently processing deferred order-dependent memory

A method and device for tracking a bus transaction between first and second agents coupled to a bus includes issuing a request for the transaction by the first agent, storing information regarding the transaction in a buffer, and deleting the information regarding the transaction from the buffer if the first agent receives an indication that the second agent will not issue a retry.

Method and apparatus for tracking bus transactions

Bootstrap processor selection architecture in SMP systems

A multiprocessor computer system that includes an emulation feature for lowest priority processor software compatibility while providing fault tolerance includes first and second processors coupled to a system bus that handles transmission of interruption messages within the system. An instruction resulting in an interruption which specifies an interrupt feature causes microcode to generate a trap. A trap handling routine reads ID information from a register of the first processor, and places it in a target processor ID field of an interruption message which gets broadcast on the system bus. The first processor eventually accepts the interruption message and is designated as the processor in the system which handles the interruption.

Emulation of interrupt control mechanism in a multiprocessor system

An I/O agent delivers the interrupt message through a chipset to a system bus connected to a number of processors. The interrupt message includes the transaction type and a destination identification. The servicing processor on the system bus matches the destination identification with its own identification to determine if it is the intended recipient of the interrupt message. The I/O agent writes the data associated with the interrupt into the buffer queue inside the chipset. The chipset automatically flushes the contents of the buffer queue to the main memory before the interrupt message is delivered. The interrupt delivery mechanism avoids complexity and delay in handshaking operations between the chipset and the I/O agent.

Mechanism for delivering interrupt messages

An improved APIC controller which utilizes an improved addressing mechanism for interrupts which provides an additional bit position for priority values so that thirty-two levels of priority may be furnished at sequential addresses within an interrupt vector table in memory. In one embodiment, circuitry is furnished which allows the alternative implementation of either a prior art addressing mechanism or the improved addressing mechanism.

Method and apparatus for providing an enhanced programmable priority

A process for generating an interrupt of programmable priority for a piece of embedded hardware associated with a first interrupt controller providing interrupts for a processor having a priority which is not programmable in a computer system including a second interrupt controller providing interrupts for the processor having a priority which is programmable. The process for causing the interrupts furnished by the first controller for the embedded hardware device to have programmable priority including the steps of generating a general interrupt at the output of the first interrupt controller in response to a signal to the first processor from the associated embedded hardware device, transferring the general interrupt to the second interrupt controller, responding to the general interrupt by signaling the associated processor that a general interrupt has been received by the second interrupt controller from the first interrupt controller, determining from the first interrupt controller the particular embedded hardware device which caused the generation of the general interrupt, and selecting an interrupt handier routine from memory for the particular embedded hardware device to provide an interrupt vector for the particular embedded hardware device to the second interrupt controller.

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Sunnyvale, CA, United States of America

Muthurajan Jayakumar