International Business Machines Corporation

Globalfoundries Inc.

Lam Research Corporation

Advanced Micro Devices Corporation

Stmicroelectronics Gmbh

Intermolecular, Inc.

Elpis Technologies Inc.

Muthumanickam Sankarapandian

Sampath Purushothaman

Elbert Emin Huang

Sanjay C Mehta

Yann Mignot

Matthew Earl Colburn

Kangguo Cheng

Balasubramanian Pranatharthiharan

Zhenxing Bi

Chi-Chun Liu

Jeffrey Curtis Hedrick

John Christopher Arnold

Yongan Xu

Ruilong Xie

Nicolas J Loubet

Robert Dennis Miller

Stephen McConnell Gates

Terry Allen Spooner

Satyanarayana Venkata Nitta

Willi Volksen

Tenko Yamashita

Injo Ok

Hosadurga K Shobha

Indira P Seshadri

Nicole A Saulnier

Christy Sensenich Tyberg

David V Horak

James L Hedrick

Steven J Holmes

Shom Ponoth

Ruqiang Bao

Soon-Cheon Seo

Ekmini Anuja De Silva

Su Chen Fan

Andrew Herbert Simon

Dirk Pfeiffer

Yunpeng Yin

David Lee Rath

Kevin W Brew

Ho-Cheol Kim

Vimal Kumar Kamineni

Teddie Peregrino Magbitang

Kaushik Arun Kumar

Linda Karin Sundberg

Victor Yee-Way Lee

Kelly Malone

Brent A Anderson

Theodorus E Standaert

Daniel C Edelstein

Chun-chen Yeh

Vijay Narayanan

Michael A Guillorn

Alfred Grill

Hsueh-Chung Chen

Hiroaki Niimi

John Anthony Fitzsimmons

Griselda Bonilla

John Ryan Sporre

Nelson M Felix

Chun Wing Yeung

Sean David Burns

Christopher Joseph Waskiewicz

Michael P Belyansky

Timothy A Brunner

James John Kelly

William J Cote

Ankit Vora

Jing Guo

Alexander Reznicek

Chih-Chao Yang

Bruce Bennett Doris

Junli Wang

Chanro Park

Keith E Fogel

Oleg Gluschenkov

Hemanth Jagannathan

Ajey Poovannummoottil Jacob

Son Van Nguyen

Fee Li Lie

Jingyun Zhang

Xiuyu Cai

Zuoguang Liu

Hong He

Oscar Van Der Straten

Kisik Choi

Koji Watanabe

Steven J Bentley

Gauri V Karve

Donald Francis Canaperi

Richard Anthony Conti

Anna Wanda Topol

Pierre Morin

Shyng-Tsong Chen

Bruce Kenneth Furman

Murat Kerem Akarvardar

Dexin Kong

Raghuveer Reddy Patlolla

Joe Lee

Charan V Surisetty

John S Foster

A method of manufacturing a semiconducting device that includes forming first opening for forming bottom electrode hole in a first area of a semiconductor wafer; forming a deeper second opening for overlay/alignment hole in second area; depositing a bottom electrode metal layer filling the first opening to form a bottom electrode and partially filling the second opening. A layer of sacrificial material is then deposited above the bottom electrode layer and completely filling the second opening. A chemical-mechanical planarization process is performed to remove the -bottom electrode metal and -sacrificial layer, the -sacrificial material layer being removed above a surface defined atop the filled remaining portion above the second opening. The sacrificial layer material is removed in the remaining portion of the second opening. The second opening providing an overlay/alignment feature topography detectable for alignment by lithography and for overlay measurement on the overlay metrology tool.

Maskless alignment scheme for BEOL memory array manufacturing

A semiconductor structure comprises a plurality of gate structures alternately stacked with a plurality of channel layers, and a plurality of spacers disposed on lateral sides of the plurality of gate structures. The respective ones of the plurality of spacers comprise a profile having a first portion comprising a first shape and a second portion comprising a second shape, wherein the first shape is different from the second shape.

Inner spacer formation for nanosheet transistors

A phase change memory bridge cell comprising a dielectric layer located on top of a at least one electrode, wherein a trench is located in the dielectric layer. A first liner located at the bottom of the trench in the dielectric layer and the first liner is located on the sidewalls of the dielectric layer that forms the sidewalls of the trench. A phase change memory material located on top of the first liner, wherein a top surface of the phase change memory material is aligned with a top surface of the dielectric layer, wherein the dielectric layer is located adjacent to and surrounding the vertical sidewalls of the phase change memory material, wherein a top surface of the phase change memory material is flush with a top surface of the dielectric layer.

Confined bridge cell phase change memory

A phase change memory (PCM) cell includes an electrode, a heater electrically connected to the electrode, a PCM material electrically connected to the heater, a second electrode electrically connected to the PCM material, an electrical insulator surrounding the PCM material, and a shield positioned between the PCM material and the electrical insulator, the shield comprising a reactive-ion-etching-resistant material.

Phase change memory cell spacer

A semiconductor device includes a stack structure having at least first, second and third interconnect levels. Each interconnect level has a patterned metal conductor including a first metallic material. A via spans the second and third interconnect levels and electrically couples with the patterned metal conductor of the first interconnect level. At least a segment of the super via includes a second metallic material different from the first metallic material.

Metal via structure

A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least a first channel region and a second channel region. The first channel region and the second channel region each include metal gate structures surrounding a different nanosheet channel layer. The metal gate structures of the first and second channel regions are respectively separated from each other by an unfilled gap. The method includes forming a gap fill layer between and in contact with gate structures surrounding nanosheet channel layers in multiple channel regions. Then, after the gap fill layer has been formed for each nanosheet stack, a masking layer is formed over the gate structures and the gap fill layer in at least a first channel region. The gate structures and the gap fill layer in at least a second channel region remain exposed.

Enabling residue free gap fill between nanosheets

A semiconductor structure may include a heater surrounded by a dielectric layer, a projection liner on top of the heater, a phase change material layer above the projection liner, and a top electrode contact surrounding a top portion of the phase change material layer, The projection liner may cover a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer and the heater. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The top electrode contact may be separated from the phase change material layer by a metal liner. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.

Phase change memory cell with a wrap around and ring type of electrode contact and a projection liner

A vertical transport fin field effect transistor (VT FinFET), including one or more vertical fins on a surface of a substrate, an L-shaped or U-shaped spacer trough on the substrate adjacent to at least one of the one or more vertical fins, and a gate dielectric layer on the sidewalls of the at least one of the one or more vertical fins and the L-shaped or U-shaped spacer trough.

Approach to bottom dielectric isolation for vertical transport fin field effect transistors

A phase change material memory device is provided. The phase change material memory device includes one or more electrical contacts in a substrate, and a dielectric cover layer on the electrical contacts and substrate. The phase change material memory device further includes a lower conductive shell in a trench above one of the one or more electrical contacts, and an upper conductive shell on the lower conductive shell in the trench. The phase change material memory device further includes a conductive plug filling the upper conductive shell. The phase change material memory device further includes a liner layer on the dielectric cover layer and conductive plug, and a phase change material block on the liner layer on the dielectric cover layer and in the trench.

Phase change memory device

Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first layer of the multi-layered IC structure, wherein the first layer includes a trench having a liner and a conductive interconnect formed in the trench. The liner is formed such that it is not on a portion of a sidewall of the conductive interconnect. A multi-segmented cap is formed having a first cap segment and a second cap segment. The first cap segment is on a top surface of the conductive interconnect, and a first portion of the second cap segment is on the portion of the sidewall of the conductive interconnect. The second cap segment is on a top surface of the first cap segment.

Contacts and liners having multi-segmented protective caps

A method for fabricating a semiconductor device includes forming first and second interconnect levels on a substrate with the first and second interconnect levels having respective first and second dielectric layers and first and second patterned metal conductors and where each of the first and second patterned metal conductors includes a first metallic material, depositing a third dielectric layer onto the second first interconnect layer, forming a via opening extending through the third dielectric layer and the second dielectric layer and connecting with the first patterned metal conductor of the first interconnect level and depositing a second metallic material different from the first metallic material into the via opening to form a via The via electrically couples with the patterned metal layer of the first interconnect level.

A semiconductor device includes a first transistor including a first vertical fin arranged between first bottom source or drain (S/D) region and first top S/D region, and a first recessed gate stack arranged on a sidewall of the first vertical fin. A second transistor includes second vertical fin arranged between a second bottom S/D region and second top S/D region, and a second recessed gate stack arranged on a sidewall of the second vertical fin. A first spacer contacts the sidewall of the first vertical fin and on the first recessed gate stack or the second recessed gate stack. A second spacer contacts the first spacer of the first transistor or the second transistor. The second spacer is on a sidewall of the top S/D region of the first transistor or second transistor. The inner spacer and the outer spacer include different materials.

Uniform work function metal recess for vertical transistor complementary metal oxide semiconductor technology

Self-aligned gate/junction for VTFET devices are provided. In one aspect, a method of forming a VTFET device includes: forming a stack on a wafer including a first c-SiGe layer, a c-Si layer, and a second c-SiGe layer, wherein the first c-SiGe layer serves as a bottom source/drain; forming fin hardmasks on the stack; partially recessing the second c-SiGe layer to form a fin(s) in the second c-SiGe layer, wherein the second c-SiGe layer that is partially recessed/fin(s) serve as a top source/drain; amorphizing the c-Si layer to form a-Si regions in between c-Si regions that serve as vertical channels; selectively removing the a-Si regions to form gate trenches; forming bottom/top spacers in the gate trenches; and forming gates in the gate trenches that are offset from the bottom/top source/drain by the bottom/top spacers. A VTFET device is also provided. The VTFET device is suitable for 3D monolithic integrated circuits.

Self-aligned gate and junction for VTFET

A method is presented for forming interlayer connections in a semiconductor device. The method includes patterning an etch stack to provide for a plurality of interlayer connections, etching guide layers following the etch stack to a first capping layer to form a plurality of guide openings, concurrently exposing a first plurality of conductive lines and a second plurality of conductive lines to form a plurality of interlayer connection openings by etching through the plurality of guide openings to remove the first capping layer, an interlayer dielectric, and a second capping layer, and depositing a metal fill in the plurality of interlayer connection openings to form the plurality of interlayer connections.

Svia using a single damascene interconnect

A method for semiconductor processing includes removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure. A top layer of the trilayer structure in a second region of the semiconductor device is removed during the removal of the bottom layer in the first region. The method further includes, after removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure.

Removal of trilayer resist without damage to underlying structure

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Niskayuna, NY, United States of America

Muthumanickam Sankarapandian