Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Tahoe Research, Ltd.

Muthukumar Swaminathan

Raj K Ramanujan

Taarinya Polepeddi

Mohan J Kumar

Bill Nale

Tessil Thomas

David Zimmerman

Glenn J Hinton

Dimitrios Ziakas

Bassam N Coury

Kunal A Khochare

Rajat Agarwal

Rajesh Sundaram

Richard Paul Mangold

Camille C Raad

Prashant S Damle

Zhe Wang

Philip Hillier

Jeffrey W Ryden

Murugasamy K Nachimuthu

Mahesh S Natu

Kai Cheng

Zion S Kwok

Alaa R Alameldeen

Doyle W Rivers

Robert S Chappell

Lidia Warnes

James W Alexander

Zeshan A Chishti

Rajesh S Parthasarathy

Adrian C Moga

Wayne Alan Downer

Madhavan Parthasarathy

Larry O Smith

Andy M Rudoff

Jason A Gayman

Daniel K Osawa

Scott J Cape

Maciej Plucinski

David J Zimmerman

Wayne A Downer

Examples include updating firmware for a persistent memory module in a computing system during runtime. Examples include copying a new version of persistent memory module firmware into an available area of random-access memory (RAM) in the persistent memory module, and transferring processing of a current version of persistent memory module firmware to the new version of persistent memory module firmware during runtime of the computing system, without a reset of the computing system and without quiesce of access to persistent memory media in the persistent memory module, while continuing to perform critical event handling by the current version of persistent memory module firmware. Examples further include initializing the new version of persistent memory module firmware; and transferring processing of critical event handling from the current version of persistent memory module firmware to the new version of persistent memory module firmware when initializing the new version of persistent memory module firmware is completed.

Memory device firmware update and activation without memory access quiescence

Embodiments are directed towards apparatuses, methods, and systems including a pre-read command to eliminate an additional access of read data from a storage location of a memory device. In embodiments, a memory controller issues a pre-read command to store read data in a pre-read latch. In embodiments, the command is issued during a first access of the read data from a storage location in connection with a modify-write operation of the read data. In embodiments, the pre-read latch is located in or coupled to a selected partition of a memory device that includes the storage location that stores the read data. In embodiments, the memory controller subsequently issues a modify-write command to compare the read data stored in the pre-read latch with incoming data, to eliminate a need for a second access of the storage location during completion of the modify-write operation. Additional embodiments may be described and claimed.

Apparatuses, systems, and methods to store pre-read data associated with a modify-write operation

A two-level main memory that includes a persistent memory and a cache is provided. Locations of dirty cache lines in the cache are tracked through the use a dirty cache line tracker. The dirty cache line tracker is stored in the cache and can be cached in a memory controller for the persistent memory. The dirty cache line tracker can be used to bypass cache lookup, perform efficient dirty cache line scrubbing and to decouple battery power and capacity of the cache in the two-level main memory.

Method and apparatus to efficiently track locations of dirty cache lines in a cache in a two-level main memory

A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as 'far memory.' Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as 'near memory.'

Apparatus and method for implementing a multi-level memory hierarchy

A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.

Memory channel that supports near memory and far memory access

Data reliability and integrity may be compromised when memory resources used to store the data reach elevated temperatures. A sensor in the memory resource may monitor the temperature of the memory resource in real-time. A comparator in the memory resource may indicate a high temperature condition to a memory controller. The memory controller, in response to the high temperature condition, can restrict or halt data flow to the memory resource. When the real-time temperature of the memory resource falls below a defined threshold, the memory controller may resume data flow to the memory resource.

Thermal monitoring of memory resources

Technologies for issuing commands on selected memory devices includes an apparatus that includes a data storage controller and multiple non-volatile, write in place, byte or block addressable memory devices. The memory devices are arranged in one or more ranks, and the memory devices in each rank are connected to a same communication channel. The data storage controller is to select a subgroup of the plurality of the memory devices in a rank without modifying an identifier of each memory device, and issue a command to operate on data of the selected subgroup.

Technologies for issuing commands on selected memory devices

Provided are an apparatus, system and method to determine whether to use a low or high read voltage. First level indications of write addresses, for locations in the non-volatile memory to which write requests have been directed, are included in a first level data structure. For a write address of the write addresses having a first level indication in the first level data structure, the first level indication of the write address is removed from the first level data structure and a second level indication for the write address is added to a second level data structure to free space in the first level data structure to indicate a further write address. A first voltage level is used to read data from read addresses mapping to one of the first and second level indications in the first and the second level data structures, respectively. A second voltage level is used to read data from read addresses that do not map to one of the first and the second level indications the first and second level data structures, respectively.

Apparatus, system, and method to determine a demarcation voltage to use to read a non-volatile memory

One embodiment provides a memory controller. The memory controller includes a memory controller memory; a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a current timer index from a timer circuitry in response to an initiation of a periodic patrol scrub and to compare the current timer index to a stored timestamp. The VDM selection circuitry is to update a state of a sub-block of a memory array, if the state is less than a threshold and a difference between the current timer index and the stored timestamp is nonzero. The timestamp circuitry is further to store the current timer index as a new timestamp.

Time tracking with patrol scrub

A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol

A method is described. The method includes receiving an indication of an activity of load circuitry of a power supply. The method includes, in response to the indication, generating a first signal that describes the activity and a second signal that describes whether the event is initiating or completing. The method includes determining a weight amount from the first signal and adjusting a credit count by the weight amount up or down based on the second signal. The method includes comparing the credit count against a first threshold. The method includes calculating an average credit count that accounts for the credit count and previous credit counts and comparing the average credit count against a second threshold. The method includes adjusting an activity level of the load circuitry if either threshold is crossed.

Power management circuit with per activity weighting and multiple throttle down thresholds

In response to a write operation on a storage element in a non-volatile memory device, a count provided by a global counter is stored to indicate a time at which the write operation occurs on the storage element. In response to receiving a request perform a read operation on the storage element, a determination is made of a demarcation voltage to apply for performing the read operation on the storage element, based on a progress of the global counter since the write operation on the storage element.

Determining demarcation voltage via timestamps

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Folsom, CA, United States of America

Muthukumar Swaminathan