Cypress Semiconductor Corporation

Camgian Microsystems Corp.

Muthukumar Nagarajan

Jeffery Scott Hunt

David Robert Lindley

Andrew L Hawkins

Ajay Srikrishna

Derrick J Savage

Gary Butler

George M Ansel

Justin Philpott

Jun Li

Michael David Fliesler

Morgan Andrew Whately

Jeffrey William Waldrip

Vinod Rajan

The present invention relates generally to a system and method of networking and interconnecting a large number of various types of sensors to a remote location in an efficient manner Specifically, the invention utilizes a flexible, configurable, scalable and power-efficient sensor interface relay architecture to gather sensor data from various locations and then relay it to a remote location via the internet.

Multiple sensor data processor interface and relay

The present invention relates generally to a system and method of networking and interconnecting a large number of various types of sensors to a remote location in an efficient manner. Specifically, the invention utilizes a flexible, configurable, scalable and power-efficient sensor interface relay architecture to gather sensor data from various locations and then relay it to a remote location via the internet.

Disclosed is a dynamic detector to detect an environmental condition including a power-supply level relative to a predetermined threshold signal during a training phase; and an adjustable buffer, coupled with the dynamic detector, configured to adjust output drive strength during the training phase in response to the detected environmental condition.

Method and apparatus for dynamically detecting environmental conditions and adjusting drive strength in response to the detecting

A method and apparatus to provide electrostatic discharge (ESD) protection to electronic circuits using a gate clamp circuit.

Cascode active shunt gate oxide protect during electrostatic discharge event

Cascode active shunt gate oxide project during electrostatic discharge event

An apparatus comprising one or more input/output circuits that may be configured as (i) high voltage tolerant in response to a first state of a control input and (ii) a clamp to a power supply voltage in response to a second state of said control input.

Configurable PCI clamp or high voltage tolerant I/O circuit

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first control signal and a second control signal in response to (i) a first input signal, (ii) a second input signal and (iii) a voltage control signal. The second circuit configured to generate (i) an output signal in response to the first and the second control signals and (ii) the voltage control signal in response to a pad voltage.

Multiple power supply output driver

A method and apparatus for greatly simplifying the circuitry needed to handle the bubbleback situations in FIFO memories includes an additional row of cells added to the memory array. By adding an extra row of memory cells, the read and write pointer are only on the same row when the FIFO is operating near the empty boundary or in fallthrough mode.

Bubbleback for FIFOS

A method and apparatus for writing data onto the read bitline when a FIFO buffer memory is nearly empty that includes circuitry detecting when a memory is nearly empty, when the read pointer and the write pointer are on the same line with the read pointer behind the write pointer. Another circuit writes data onto the read bitline as the data is written into the buffer memory.

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Starkville, MS, United States of America

Muthukumar Nagarajan