Hitachi Global Storage Technologies Netherlands B.v.

International Business Machines Corporation

Spin Memory, Inc.

Integrated Silicon Solution, (cayman) Inc.

Spin Transfer Technologies, Inc.

Solopower, Inc.

Hgst Netherlands, B.v.

Hitachi Global Storage Technologies

Solopower Systems, Inc.

Other

Hitachi Gloabl Storage Technolgies Netherlands B.v.

Hitachi Global Storage Technologies Amsterdam

Mustafa Pinarbasi

James Mac Freitag

Bartlomiej Adam Kardasz

Thomas D Boone

Jorge Vasquez

Hardayal Singh Gill

Patrick Rush Webb

Pradeep Manandhar

Manfred Ernst Schabes

Kuok San Ho

Jacob Anthony Hernandez

Ching Hwa Tsang

Georg Wolf

Wipul Jayasekara

Elizabeth Ann Dobisz

Howard Gordon Zolla

Serdar Aksu

Yuan-Tung Chin

Bulent Mehmet Basol

Richard Hsiao

Michael Andrew Parker

Hua Ai Zeng

Cheng Wei Chiu

Girish Jagtini

Phong V Chau

Bartek Kardasz

Kim Yang Lee

Marcin Gajek

Michail Tzoufras

Prachi Shrivastava

Son Van Nguyen

Quang Le

Mohamad Towfik Krounbi

Ashok Lahiri

Paul Phong Nguyen

Kadriye Deniz Bozdag

Jih-Shiuan Luo

Robert Otto Schwenker

Tsung Yuan Chen

Michael R Feldbaum

David Eugene Heim

Marie-Claire Cyrille

Alfred Floyd Renaldo

Serhat Metin

Girish Jagtiani

Parshuram Balkrishna Zantye

Pirachi Shrivastava

Arindom Datta

Dwight Cornwell, Jr

Mao-Min Chen

Jeffrey Childress

Tsann Lin

Andrew J Walker

Stefan Maat

Matthew Joseph Carey

Dafna Beery

Randall George Simmons

Chun-Ming Wang

Douglas Johnson Werner

Jyh-Shuey Jerry Lo

Frederick Hayes Dill

Yuriy Borisovich Matus

Prakash Kasiraj

Ian Robson McFadyen

Eric Ryan

James Lamar Nix

Wen-yaung Lee

Ciaran Avram Fox

Jiaxiong Wang

Robert Langland Smith

Richard Jule Contreras

Mary Kathryn Gutberlet

Hamid Balamane

Rasmi R Das

Jacqueline K Latimer

Wipul Pemsiri Jayasckara

Raymond Bus-Kwofie

Lichiao Metin

Steven Watts

A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic structure in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate. The precessional spin current magnetic layer a first and second precessional spin current ferromagnetic layer separated by a nonmagnetic precessional spin current insertion layer.

Precessional spin current structure with non-magnetic insertion layer for MRAM

A method for manufacturing a magnetic memory array provides back end of line annealing for associated processing circuitry without causing thermal damage to magnetic memory elements of the magnetic memory array. An array of magnetic memory element pillars is formed on a wafer, and the magnetic memory elements are surrounded by a dielectric isolation material. After the pillars have been formed and surrounded by the dielectric isolation material an annealing process is performed to both anneal the memory element pillars to form a desired grain structure in the memory element pillars and also to perform back end of line thermal processing for circuitry associated with the memory element array.

Method for manufacturing a magnetic random-access memory device using post pillar formation annealing

Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a semiconductor comprises: a first device at a first semiconductor level within a multi terminal device stack; wherein the first device is coupled to a first terminal; a second device at a second semiconductor level within the multi terminal device stack, wherein the second device is coupled to a second terminal; a third terminal is coupled to the second device and a fourth terminal is coupled to the first device, wherein the first terminal and second terminal are independently coupled to the first device and second device respectively. The first terminal, the second terminal, the third terminal and the fourth terminal couple components included in the multi terminal stack to components not included in the multi terminal stack.

Multi terminal device stack systems and methods

The disclosure provides a magnetic random access memory element. The magnetic random access memory element includes a magnetic reference layer, a magnetic free layer, and a non-magnetic barrier layer between the magnetic free layer and the magnetic reference layer. The magnetic random access memory element further includes a MgO layer contacting the magnetic free layer. The MgO layer includes multiple homogeneous layers of MgO that provide excellent interfacial perpendicular magnetic anisotropy to the magnetic free layer while also having a low RA.

High retention storage layer using ultra-low RA MgO process in perpendicular magnetic tunnel junctions for MRAM devices

A magnetic memory element has a Ru hard mask layer. The use of Ru advantageously allows for closer spacing of adjacent magnetic memory elements leading to increased data density. In addition, the use of Ru as a hard mask reduces parasitic electrical resistance by virtue of the fact that Ru does not oxidize in ordinary manufacturing environments. The magnetic memory element can be formed by depositing a plurality of memory element layers, depositing a Ru hard mask layer, depositing a RIEable layer over the Ru hard mask layer, and forming a photoresist mask over the hard mask layer. A reactive ion etching can be performed to transfer the image of the photoresist mask onto the RIEable layer to form a RIEable mask. An ion etching can then be performed to transfer the image of the RIAable mask onto the underlying Ru hard mask and underlying memory element layers.

Magnetic tunnel junction element with RU hard mask for use in magnetic random-access memory

Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a multi terminal fabrication process comprises: performing an initial pillar layer formation process to create layers of a multi terminal stack; forming a first device in the layers of the multi terminal stack; forming a second device in the layers of the multi terminal stack; and constructing a set of terminals comprising: a first terminal coupled to the first device, a second terminal coupled to the second device; and a third terminal coupled to the first device; wherein at least two terminals in the set of terminals are independent. The third terminal can be coupled to the second device.

Multi terminal device stack formation methods

Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a semiconductor comprises: a first device at a first semiconductor level within a multi terminal device stack; wherein the first device is coupled to a first terminal; a second device at a second semiconductor level within the multi terminal device stack, wherein the second device is coupled to a second terminal; and a third terminal is coupled to the first device, wherein the first terminal and second terminal are independently coupled to the first device and second device respectively. The third terminal can be coupled to the second device. The first terminal, the second terminal, and third terminal and couple components included in the multi terminal stack to components not included in the multi terminal stack.

A spin orbit torque memory device having a vertical transistor structure. The spin orbit torque memory device includes a magnetic memory element such as a magnetic tunnel junction formed on a spin orbit torque layer. The vertical transistor structure selectively provides an electrical current to the spin orbit torque layer to switch a memory state of the magnetic memory element. The vertical transistor structure accommodates the relatively high electrical current needed to provide spin orbit torque switching while also consuming a small amount of wafer real estate. The vertical transistor structure can include a semiconductor pillar structure surrounded by a gate dielectric layer and a gate structure such that the gate dielectric layer separates the gate structure from the semiconductor pillar.

High density spin orbit torque magnetic random access memory

A Magnetic Tunnel Junction (MTJ) device can include a second Precessional Spin Current (PSC) magnetic layer of Ruthenium (Ru) having a predetermined thickness and a predetermined smoothness. An etching process for smoothing the PSC magnetic layer can be performed in-situ with various deposition processes after a high temperature annealing of the MTJ formation.

Methods of manufacture precessional spin current magnetic tunnel junction devices

A magnetoresistive random-access memory (MRAM) is disclosed. MRAM device has a magnetic tunnel junction stack having a significantly improved performance of the free layer in the magnetic tunnel junction structure. The MRAM device utilizes a precessional spin current (PSC) magnetic layer in conjunction with a perpendicular MTJ where the in-plane magnetization direction of the PSC magnetic layer is free to rotate. The precessional spin current magnetic layer is constructed with a material having a face centered cubic crystal structure, such as permalloy.

Precessional spin current structure for MRAM

A magnetic random access memory chip having magnetic memory elements with different performance characteristics formed on the same chip. The magnetic memory elements can be magnetic random access memory elements. The memory chip can have a first set of magnetic random access chips having a first set of physical and performance characteristics formed in a first area of the sensor and a second set of magnetic random access chips having a second set of performance characteristics formed in a second area of the chip. For example, the first set of magnetic random access memory elements can have performance characteristics that match or exceed those of a non-volatile memory, whereas the second set of magnetic random access memory elements can have performance characteristic that match or exceed those of a static random access memory element.

Magnetic memory chip having nvm class and SRAM class MRAM elements on the same chip

A magnetic memory element having a Ru hard mask layer. The use of Ru advantageously allows for closer spacing of adjacent magnetic memory elements leading to increased data density. In addition, the use of Ru as a hard mask reduces parasitic electrical resistance by virtue of the fact that Ru does not oxidize in ordinary manufacturing environments. The magnetic memory element can be formed by depositing a plurality of memory element layers, depositing a Ru hard mask layer, depositing a RIEable layer over the Ru hard mask layer, and forming a photoresist mask over the hard mask layer. A reactive ion etching can be performed to transfer the image of the photoresist mask onto the RIEable layer to form a RIEable mask. An ion etching can then be performed to transfer the image of the RIAable mask onto the underlying Ru hard mask and underlying memory element layers.

Magnetic tunnel junction element with Ru hard mask for use in magnetic random-access memory

A magnetic memory element having a magnetic free layer and a magnetic reference layer with a non-magnetic barrier layer between the magnetic reference layer and the magnetic free layer. A spin current layer (which may be a precessional spin current layer) is located adjacent to the magnetic free layer and is separated from the magnetic free layer by a non-magnetic coupling layer. A material layer adjacent to and in contact with the spin current layer, has a material composition and thickness that are chosen to provide a desired effective magnetization in the spin current layer. The material layer, which may be a capping layer or a seed layer, can be constructed of a material other than tantalum which may include one or more of Zr, Mo, Ru, Rh, Pd, Hf, W, Ir, Pt and/or alloys and/or nitrides of these elements.

Precessional spin current structure for magnetic random access memory with novel capping materials

Precessional spin current structure with nonmagnetic insertion layer for MRAM

Growing community of inventors

Morgan Hill, CA, United States of America

Mustafa Pinarbasi