Micron Technology Incorporated

Stmicroelectronics Gmbh

Stmicroelectronics S.r.l.

Mustafa Nazmi Kaynak

Sivagnanam Parthasarathy

Patrick Robert Khayat

Kishore Kumar Muchherla

Shane G Nowell

Sampath K Ratnam

Peter Sean Feeley

Vamsi Pavan Rayaprolu

Michael Sheperek

Larry Joseph Koudele

Xiangang Luo

Jiangang Wu

Devin M Batutis

Karl David Schuh

Steven Michael Kientz

Eyal En Gad

Bruce A Liikanen

Nicholas Julian Richardson

Qisong Lin

Robert B Eisenhuth

Mark Alan Helm

William Henry Radke

James Fitzpatrick

Yoav Weinberg

Zhengang Chen

Zhenlei Shen

Akira Goda

Alessandro Risso

Jonathan Scott Parry

Aaron S Yip

Renato C Padilla

Ugo Russo

Nagendra Prasad Ganesh Rao

Zixiang Loh

Ka Leung Ling

Huai-Yuan Tseng

Dung Viet Nguyen

Phong Sy Nguyen

Niccolo' Righetti

Stefano Valle

Niccolo′ Righetti

Shayan Srinivasa Garani

Larry K Koudele

Mariano Burich

A codeword is received and stored in a first data structure to be decoded by flipping one or more of a plurality of bits over multiple iterations by a bit flip decoder, an error check is executed on the codeword, by a controller, to identify error bits from the plurality of bits, and the state of an error bit is flipped from one of the identified error bits if parity check (PC) violations associated with the error bit meet or exceed a PC violation threshold associated with a bit flip state of the error bit, where the bit flip state is selected from one of a first bit flip state with a first PC violation threshold and a second bit flip state with a second PC violation threshold different than the first PC violation threshold. The current state of the error bit is stored in a second data structure.

Iterative bit flip decoding utilizing different bit flip states

A controller decodes embedded data from a codeword determined to have errors via a soft decoding process based on a first LLR set assigned to bits of the codeword by a controller. The controller accesses a set of bit-wise redundant array of independent NAND (RAIN) parity bits from the memory device or another memory device in response to determining failure of the soft decoding process. The controller decodes the embedded data from the codeword via a first soft RAIN decoding process based on a second LLR set and the RAIN parity bits by the controller, and decodes the embedded data from the codeword via a second soft RAIN decoding process based on a third LLR set and the RAIN parity bits by the controller in response to determining failure of the first soft RAIN decoding process.

Error decoding with soft redundant array of independent NAND (RAIN)

Embodiments disclosed can include selecting a target read window budget (RWB) increase and identifying a set of aggressor memory cells. They can also include generating a list of programming level states for the set of aggressor memory cells and identifying, in the list, an entry associated with a maximum RWB increase that is greater than or equal to the target RWB increase. They can further include responsive to identifying the entry with the total number of bits associated with a maximum RWB increase that is greater than or equal to the target RWB increase, modifying a parameter of the memory access operation with the adjustment associated with the identified entry.

Managing compensation for charge coupling and lateral migration in memory devices

An amount of voltage shift is determined for one or more memory cells of a block family based on an initial reference value pertaining to the one or more memory cells and a subsequent reference value pertaining to the one or more memory cells. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.

Voltage bin calibration based on a voltage distribution reference voltage

A memory device to manage the assignment of offset voltages for read operations, and to adjust read voltages using the offset voltages. The offset voltages are dynamically adjusted by a controller during operation of the memory device in response to read errors. In one approach, a first bin of offset voltages is assigned to a first region of a storage media. The first offset voltages are used to adjust read voltages for reading a page of first memory cells in the first region. The controller determines that at least one error has occurred in reading the page. In response to determining the error, the controller determines second offset voltages that can be used to read the first memory cell without causing a read error. Based on the second offset voltages, the controller identifies third offset voltages for assigning to the first region. The third offset voltages are used for adjusting read voltages for subsequent reads of pages in the first region. The third offset voltages can be assigned from an existing offset voltage bin, or a new offset voltage bin can be generated for the assignment.

Dynamic adjustment of offset voltages for reading memory cells in a memory device

Methods, systems, and apparatuses detect and mitigate a stall condition in an iterative bit flipping decoder. A codeword is received and one or more of the bits in the codeword are flipped in each of multiple iterations of bit flipping decoding using a first set of bit flipping rules. Each of the iterations includes a determination of a syndrome weight. In response to determining a count of iterations in which the syndrome weight increased satisfies a threshold, one or more of the bits in the codeword are flipped in a subsequent iteration using a second set of bit flipping rules that differs from the first set of bit flipping rules.

Detecting a stall condition in bit flipping decoding using syndrome weight slope

A method includes performing a read operation of a first codeword including first hard data and generating an error vector using a reliability metric of the first hard data. The first hard data and error vector are stored in first and second portions of memory. A first corrected codeword is returned that combines the error vector and the hard data from the first and second portions of memory. A read operation of a second codeword is performed, including second hard data and soft information. The hard data and soft information are stored in the first and second portions of memory. A bit of second hard data is flipped responsive to comparing a reliability metric of the bit of the second hard data to a bit flipping threshold, wherein flipping the bit includes updating the second hard data. The updated second codeword is returned resulting from reading the portions of memory.

Efficient memory use to support soft information in bit flipping decoders

A method includes determining, by a processing device, a value of a memory endurance state metric associated with a segment of a memory device in a memory sub-system; determining a target value of a code rate based on the value of the memory endurance state metric, and adjusting the code rate of the memory device according to the target value, wherein the code rate reflects a ratio of a number of memory units designated for storing host-originated data to a total number of memory units designated for storing the host-originated data and error correction metadata.

Adjustment of code rate as function of memory endurance state metric

A bit flipping decoder receives a codeword stored in a memory device. The bit flipping decoder determines a plurality of energy function values for the codeword and a least reliable of the energy function values for the codeword. In response to the bit flipping decoder determining the least reliable energy function value fails to satisfy a bit flipping criterion of a current iteration, the bit flipping decoder increments an iteration count. The incrementing of the iteration count bypasses a comparison of the plurality of energy function values with the bit flipping criterion of the current iteration.

Bypassing iterations in a bit flipping decoder using a least reliable bit energy function

A of bit flipping (BF) decoder decodes codewords using a first set of BF thresholds. A first minimum number of iterations of decoding performed on the codewords is determined to achieve a first target decoding rate. Codewords are decoded using a second set of BF thresholds. The first set of BF thresholds are more likely to cause bit flips than the second set of BF thresholds. A second minimum number of iterations of decoding performed on the codewords is determined to achieve a second target decoding rate. Bits in a codeword are flipped using the first set of BF thresholds for the first minimum number of iterations. Bits are flipped in the codeword using the second set of BF thresholds in response to determining the codeword remains undecoded as a result of the first minimum number of iterations.

Bit flipping decoder with optimized maximum iterations for varied bit flipping thresholds

An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.

Block family-based error avoidance for memory devices

A processing device in a memory sub-system determines a syndrome weight for a sense word read from a memory device and determines whether the syndrome weight for the sense word satisfies a threshold criterion. Responsive to the syndrome weight for the sense word satisfying a respective threshold criterion associated with a next iteration of a first decoding operation, bypassing the first decoding operation and initiating a second decoding operation for the sense word, wherein the second decoding operation has a higher error correction capability than the first decoding operation.

Early stopping of bit-flip low density parity check decoding based on syndrome weight

A processing device in a memory sub-system monitors a temperature associated with a block of a memory device, the block comprising a plurality of wordlines. The processing device further determines a first amount of time between when memory cells associated with a first wordline of the plurality of wordlines of the block were written and when memory cells associated with a last wordline of the plurality of wordlines of the block were written. That first amount of time is normalized according to the temperature associated with the block. The processing device further determines, based at last in part on the first amount of time and on an associated scaling factor, an estimate of when the block will reach a uniform charge loss state.

Temperature-compensated time estimate for a block to reach a uniform charge loss state

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is associated with a voltage offset bin; determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and performing the error-handling to recover the data.

Managing error-handling flows in memory devices

A processing device in a memory sub-system detects an occurrence of a triggering event, determines respective levels of charge loss associated with a first representative wordline of a block of a memory device and with a second representative wordline of the block of the memory device, and determines whether a difference between the respective levels of charge loss satisfies a threshold criterion. Responsive to determining that the difference between the respective levels of charge loss satisfies the threshold criterion, the processing device further determines that the block is in a uniform charge loss state.

Measurement of representative charge loss in a block to determine charge loss state

Growing community of inventors

San Diego, CA, United States of America

Mustafa Nazmi Kaynak