Synopsys, Inc.

Google Inc.

Mustafa Ispir

Levent Oktem

Hrishikesh Balkrishna Aradhye

Gregory Sean Corrado

Tushar Deepak Chandra

Wei Chai

Tal Shaked

Jeremiah Harmsen

Glen Anderson

Rohan Anil

Xiaobing Liu

Heng-Tze Cheng

Mehmet Levent Koc

A system includes one or more computers and one or more storage devices storing instructions that when executed by the one or more computers cause the computers to implement a combined machine learning model for processing an input including multiple features to generate a predicted output for the machine learning input. The combined model includes: a deep machine learning model configured to process the features to generate a deep model output; a wide machine learning model configured to process the features to generate a wide model output; and a combining layer configured to process the deep model output generated by the deep machine learning model and the wide model output generated by the wide machine learning model to generate the predicted output, in which the deep model and the wide model have been trained jointly on training data to generate the deep model output and the wide model output.

Wide and deep machine learning models

A method for designing an integrated circuit is described. The method comprises converting behavioral descriptions of the integrated circuit to register transfer level (RTL) descriptions. The method comprises at least one of the behavioral descriptions including frame synthesis with an input frame and a corresponding output frame. In one embodiment, the method further comprises providing at least two solutions for performing partial and complete operations for simulations as hardware component combinations, associating each solution with a cost, and selecting the solution with the lowest cost as the hardware component combination for a final design of the integrated circuit.

Using entropy in an colony optimization circuit design from high level synthesis

Methods and apparatuses for retiming of multirate system for clock period minimization with a polynomial time without sub-optimality. In an embodiment, a normalized factor vector for the nodes of multirate graph is introduced, allowing the formulation of the multirate graph retiming constraints to a form similar to a single rate graph. In an aspect, the retiming constraints are formulated to allowed the usage of linear programming methodology instead of integer linear programming, thus significantly reducing the complexity of the solving algorithm. The present methodology also uses multirate constraints, avoiding unfolding to single rate equivalent, thus avoiding graph size increase. In a preferred embodiment, the parameters of the multirate system are normalized to the normalized factor vector, providing efficient algorithm in term of computational time and memory usage, without any sub-optimality.

Retiming of multirate system

A method and apparatus for improving the interconnection and multiplexing cost of circuit design from high level synthesis using ant colony optimization is described. In one example, a plurality of hardware components for performing an operation is represented with a data flow graph having edges and nodes. A plurality of solutions are simulated for performing the operation as hardware component and schedule combinations represented as paths on the data flow graph. For each solution, cost including a number of edges and nodes traversed on the data flow graph and an interconnection cost related to the number of different hardware components in the path is determined. A pheromone trail is associated with each path, the pheromone trail including a cost of the respective scheduling solution, and a solution is selected with the highest value pheromone trail as a hardware component and schedule combination for a circuit.

Method and apparatus for improving the interconnection and multiplexing cost of circuit design from high level synthesis using ant colony optimization

A method and apparatus for synthesizing pipelined input/output in a circuit design from high level synthesis is described. In one example, an operation is selected to be performed by a circuit, the operation including a plurality of partial operations of different types. The partial operations are ordered based on the ordering of the variables. A plurality of hardware components for performing the operations are represented with a data flow graph having edges and nodes, the edges and nodes being connected based on the ordering of partial operations. A plurality of solutions are simulated for performing the operations as hardware component combinations represented as paths on the data flow graph. For each solution, a cost including a number of edges and nodes traversed on the data flow graph is determined, and a solution is selected with the lowest cost as a hardware component combination for a circuit.

Method and apparatus for synthesizing pipelined input/output in a circuit design from high level synthesis

A method and apparatus for using entropy in ant colony optimization circuit design from high level synthesis is described. In one example, an operation to be performed by a circuit is selected. A plurality of hardware components for performing the operation are represented with a data flow graph having edges and nodes. A plurality of solutions for performing the operation are simulated as hardware component combinations represented as paths on the data flow graph. For each solution the cost including a number of edges and nodes traversed on the data flow graph and a supplemental sub-integer cost is determined and a solution is selected with the lowest cost as a hardware component combination for a circuit.

Method and apparatus for using entropy in ant colony optimization circuit design from high level synthesis

Methods and apparatuses to optimize a circuit representation using unfolding as a preprocessing of the multirate folding. In at least one embodiment of the present invention, a portion of a data flow graph representation of a circuit is optimized using circuit operation level before using optimizing with data flow algorithm and mapping the design onto hardware. In an aspect, the present invention discloses circuit operation level optimization for data flow graph representations with optimizing zero inputs caused by the upsamplers, or with optimizing unused outputs caused by the downsamplers. In at least one embodiment of the present invention, multirate data graph is converted to a single rate data graph before data flow optimizing. In an aspect, converting a multirate data graph to a single rate data graph comprises unfolding the multirate data graph with minimum unfolding factors that are inversely proportional to the clock values.

Growing community of inventors

Cayyolu Ankara, Turkey

Mustafa Ispir