Silicon Laboratories Inc.

Mustafa H Koroglu

Abdulkerim Coban

Ramin Khoini-Poorfard

Yu Su

Alessandro Piovaccari

Vitor Pereira

Francesco Barale

Aslamali A Rafi

Sherry Xiaohong Wu

Rangakrishnan Srinivasan

John M Khoury

David S Trager

Terry Lee Dickey

Zhongda Wang

Luigi Panseri

Sriharsha Vasadi

Ruifeng Sun

Jeffrey A Tindle

Wenhuan Yu

Michael Johnson

Krishna Pentakota

Peter Vancorenland

Pio Balmelli

Mohamed M Elkholy

Praveen Vangala

Ramin Khoini Poorfard

Yan Zhou

G Tyson Tuttle

Scott Willingham

Jing Li

Arup Mukherji

Pascal Blouin

Abhishek Kammula

Emmanuel Gautier

Euisoo Yoo

Essam S Atalla

Vinod Jayakumar

Diptendu Ghosh

Dayasagar Gaade

Eddy Bell

In one aspect, an apparatus comprises: a driver circuit to receive first and second ramp signals and output first and second drive signals under control of a first bias signal and a second bias signal, the first bias signal having a first edge and a second edge, the second edge having a different edge rate than the first edge, the second bias signal having a third edge and a fourth edge, the third edge having a different edge rate than the fourth edge; and an output circuit coupled to the driver circuit, the output circuit comprising at least one first active device to be driven by the first drive signal and at least one second active device to be driven by the second drive signal, where the output circuit is to amplify and output a radio frequency (RF) signal.

Reducing output harmonics and ground bounce in a transmitter

A transmitter including a frequency synthesizer with a voltage-controlled oscillator that provides an oscillating signal, a programmable delay circuit that delays the oscillating signal to provide a delayed oscillating signal, a power amplifier that is configured to amplify the delayed oscillating signal for transmission sufficient to produce interference, and a delay controller that programs the delay circuit with a delay time that reduces interference caused by coupling from the power amplifier to the voltage-controlled oscillator. The delay circuit may be programmed to reduce control voltage change of the voltage-controlled oscillator as a function of delay change, and/or to reduce phase noise degradation at an output of the transmitter as a function of delay change. The delay may be adjusted based on detected operating temperature. A calibration value may be determined at a calibration frequency, in which a frequency offset may be determined based on a selected channel frequency.

System and method of mitigating interference caused by coupling from power amplifier to voltage-controlled oscillator

A switching power amplifier with harmonic suppression including a polyphase converter and a power amplifier stage. The polyphase converter converts a frequency or phase modulated input signal into a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when high, and a negative 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when low. The power amplifier stage includes first and second branches coupled between upper and lower nodes, each including series-coupled P-channel and N-channel transistors forming an intermediate output node. The transistors of the first branch are controlled by the 50% duty cycle signal, and the transistors of the second branch are controlled by the positive and negative 25% duty cycle signals. The first and second branches generate output currents that are superimposed with each other to suppress third and fifth harmonics.

Switching power amplifier with output harmonic suppression

A transmitter including a frequency synthesizer with a voltage-controlled oscillator that provides an oscillating signal, a programmable delay circuit that delays the oscillating signal to provide a delayed oscillating signal, a power amplifier that is configured to use the delayed oscillating signal for transmitting a signal, and a delay controller that programs the delay circuit with a delay time that reduces interference caused by coupling from the power amplifier to the voltage-controlled oscillator. The delay circuit may be programmed to reduce control voltage change of the voltage-controlled oscillator as a function of delay change, and/or to reduce phase noise degradation at an output of the transmitter as a function of delay change. The delay may be adjusted based on detected operating temperature. A calibration value may be determined at a calibration frequency, in which a frequency offset may be determined based on a selected channel frequency.

A wireless transceiver including a receiver circuit coupled to an RF transceiver node, a tunable notch filter coupled between the RF transceiver node and a reference node, and a controller that programs the tunable notch filter with a selected blocker frequency and that selectively enables the tunable notch filter to attenuate at least one blocker signal. The tunable notch filter may include a variable capacitor and an inductor coupled in series between the RF transceiver node and ground. The inductor of the tunable notch filter may include a bondwire coupled between a semiconductor die and a semiconductor package. The inductance may include a physical inductor mounted on the package or a printed circuit board. The tunable notch filter may be enabled by a switch selectively coupling the filter to either the RF transceiver node or ground. The variable capacitor may be digitally programmed with digital values stored in a memory.

Frequency selective attenuator for optimized radio frequency coexistence

A phase-locked loop (PLL) that provides a local oscillator signal for a radio. An oscillator of the PLL supplies an oscillator output signal. Control logic receives a request to change the oscillator output signal to a new frequency and responds to the request by setting a first capacitor circuit of the oscillator to a first capacitance that corresponds to a predetermined frequency of the oscillator output signal. The control logic also responds to the request by setting one or more other capacitor circuits of the oscillator according to temperature and according to a frequency difference between the predetermined frequency and the new frequency. After responding to the request by setting the first capacitor circuit and the one or more other capacitor circuits, the PLL locks to the new frequency using a signal from the PLL loop filter to adjust another capacitor circuit in the oscillator.

Fast frequency synthesizer switching

A bias circuit for a low noise amplifier of a front end interface of a radio frequency communication device including a bias generator providing a bias voltage on a bias node for the low noise amplifier, a first resistive device coupled between the bias node and an input of the low noise amplifier, a first switch coupled in parallel with the first resistive device, and mode control circuitry receiving a mode signal indicative of a mode change, in which the mode control circuitry, in response to a mode change, momentarily activates the first switch to bypass the first resistive device and momentarily increases current capacity of the bias generator. The mode control circuitry may also momentarily activate a second switch to bypass a second resistive device of the bias circuit. The mode control circuitry may increase a sink current of the bias generator in response to the mode change.

Bias circuit for a low noise amplifier of a front end interface of a radio frequency communication device that enables fast transitions between different operating modes

A frequency synthesizer on an integrated circuit provides a local oscillator (LO) signal for RF operations and also functions as an injection clock signal source during crystal oscillator startup. The integrated circuit goes into a sleep mode in which the crystal oscillator is off and responsive to a wakeup event the crystal oscillator starts up again using the injection clock signal sourced from the frequency synthesizer. Parameters that cause the injection clock signal to match the crystal oscillator frequency are stored. The frequency synthesizer includes a phase-locked loop having an LC oscillator. A digital to analog converter controls the LC oscillator during injection. During an initial power up of the integrated circuit, a PLL in the frequency synthesizer locks to the crystal oscillator frequency to determine the parameters to store for injection.

Utilizing the LC oscillator of a frequency synthesizer as an injection source for crystal oscillator startup

An apparatus includes a radio-frequency (RF) circuit, which includes a power amplifier coupled to receive an RF input signal and to provide an RF output signal in response to a modified bias signal. The RF circuit further includes a bias path circuit coupled to modify a bias signal as a function of a characteristic of an input signal to generate the modified bias signal. The bias path circuit provides the modified bias signal to the power amplifier.

Apparatus for radio-frequency amplifier with improved performance and associated methods

A wireless transceiver circuit with an impedance matching network within an integrated circuit is disclosed. In some embodiments, the impedance matching network utilizes an inductor, having two portions, disposed on two different metal layers of the integrated circuit. The first end of the first portion of the inductor is in communication with an antenna. The second end of the second portion is in communication with a low noise amplifier for receiving signals and a power amplifier for transmitting RF signals. The second end of the first portion is connected to the first end of the second portion using a via. In another embodiment, the two portions are disposed on the same metal layer, wherein one portion is disposed within the other with a gap separating the two portions. These configurations require less space than using two separate inductors and also have a low coupling coefficient.

Low loss impedance matching circuit network having an inductor with a low coupling coefficient

A wireless device including a receiver circuit coupled to a radio frequency receiver node, a frequency selective attenuator including an inductor and a first capacitor coupled in series to the radio frequency receiver node, and a second capacitor coupled in parallel with the first capacitor. The first capacitor has a first capacitance based on a blocker frequency and the second capacitor has a second capacitance that linearizes the frequency selective attenuator. A method of linearizing a frequency selective attenuator including detecting presence of a blocker signal, activating and programming a capacitor of the frequency selective attenuator to reduce a strength of the blocker signal, determining a frequency difference between the blocker signal and a receive frequency, and coupling a second capacitor to the frequency selective attenuator to linearize the frequency selective attenuator when the frequency difference is no more than an attenuation threshold.

Dynamically reconfigurable frequency selective attenuator for radio frequency receiver front end

Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. For disclosed embodiments, a filter circuit is coupled between a first internal node and a connection pad for an integrated circuit. The filter circuit includes a first inductance, a variable capacitance, and a second inductance. The capacitance amount for the variable capacitance is controlled to tune filtering for the filter circuit to a harmonic of a frequency for a transmit output signal. A power amplifier outputs the transmit output signal to the connection pad without passing through the filter circuit. The filter circuit filters the harmonic of the frequency for the transmit output signal, shunting harmonic current to ground. For one embodiment, the filtered harmonic is a third harmonic of the transmit frequency. For one embodiment, the transmit output signal has an output power greater than or equal to 15 dBm.

Harmonic filtering for high power radio frequency (RF) communications

In an embodiment, an apparatus includes: a modulator to modulate a first signal; a distortion circuit coupled to the modulator to digitally pre-distort the first signal to compensate for a distortion of an amplifier; a distortion characterization circuit coupled to the distortion circuit to determine the distortion of the amplifier and configure the distortion circuit based on the determined distortion; a mixer coupled to the distortion circuit to upconvert the pre-distorted first signal to a pre-distorted radio frequency (RF) signal; and the amplifier coupled to the mixer to amplify the pre-distorted RF signal and output an amplified RF signal.

Radio frequency power amplifier adaptive digital pre-distortion

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Austin, TX, United States of America

Mustafa H Koroglu