Synopsys, Inc.

Other

Magma Design Automation, Inc.

Mustafa Celik

Jiayong Le

Ayhan Mutlu

Guy Maor

Lawrence Thomas Pileggi

Xin Liang Li

Ronald Alan Rohrer

The invention provides a method for performing statistical static timing analysis using a novel on-chip variation model, referred to as Sensitivity-based Complex Statistical On-Chip Variation (SCS-OCV). SCS-OCV introduces complex variation concept to resolve the blocking technical issue of combining local random variations, enabling accurate calculation of statistical variations with correlations, such as common-path pessimism removal (CPPR). SCS-OCV proposes practical statistical min/max operations for random variations that can guarantee pessimism at nominal and targeted N-sigma corner, and extends the method to handle complex variations, enabling graph-based full arrival/required time propagation under variable compaction. SCS-OCV provides a statistical corner evaluation method for complex random variables that can transform vector-based parametric timing information to the single-value corner-based timing report, and based on the method derives equations to bridge POCV/SSTA with LOCV. This significantly reduces the learning curve and increases the usage of the technology, being more easily adopted by the industry.

Statistical corner evaluation for complex on-chip variation model

Statistical corner evaluation for complex on chip variation model

The electrical circuit timing method provides accurate nominal delay together with the delay sensitivities with respect to different circuit elements (e.g., cells, interconnects, etc.) and variational parameters (e.g., process variations; environmental variations). All the sensitivity computations are based on closed-form formulas; as a consequence, the method provides rapidly and at low cost high accuracy and high numerical stability.

Statistical delay and noise calculation considering cell and interconnect variations

Sensitivity-based complex statistical modeling for random on-chip variation

The electrical circuit timing method provides accurate nominal delay together with the delay sensitivities with respect to different circuit elements {e.g., cells, interconnects, etc.) and variational parameters (e.g., process variations; environmental variations). All the sensitivity computations are based on closed-form formulas; as a consequence, the method provides rapidly and at low cost high accuracy and high numerical stability.

The large-scale process and environmental variations for today's nano-scale ICs are requiring statistical approaches for timing analysis and optimization (). Significant research has been recently focused on developing new statistical timing analysis algorithms (), but often without consideration for how one should interpret the statistical timing results for optimization. The invention provides a sensitivity-based metric () to assess the criticality of each path and/or arc in the statistical timing graph (). The statistical sensitivities for both paths and arcs are defined. It is shown that path sensitivity is equivalent to the probability that a path is critical, and arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability () is described for fast sensitivity computation that has a linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples.

Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations

A system and a method are disclosed for performing a timing or signal propagation delay analysis on a circuit. The disclosure includes representing a drive logic stage as a representative linear circuit driven by a current source. The current source is represented as a function of a current at a constant value, a start time, a tail-start time, and a time constant of an equivalent capacitive circuit. Once the current source model is constructed, a logic stage can be analyzed for timing or signal propagation delay using conventional linear circuit analysis techniques. The disclosure also is applicable to resistance capacitance ('RC') interconnect circuits using a current source model in which an RC load is represented as an effective capacitance and the current source for use in a linear analysis is constructed using an iterative approach.

Growing community of inventors

Santa Clara, CA, United States of America

Mustafa Celik