Qualcomm Incorporated

Imec

Imec Vzw

Interuniversitair Microelektronica Centrum (imec)

Mustafa Badaroglu

Jeffrey Xu

Stanley Seungchul Song

Choh Fei Yeap

Vladimir Machkaoutsan

Da Yang

John Jianhong Zhu

Kern Rim

Zhongze Wang

Junjing Bao

Matthew Michael Nowak

Niladri Mojumder

Kangho Lee

Chando Park

Yu Lu

Matthias Georg Gottwald

Jimmy Jianan Kan

Periannan Chidambaram

Julien Ryckaert

Xiaonan Chen

Naoto Horiguchi

Lars-Ake Ragnarsson

Erik Jan Marinissen

Tom Schram

Yandong Gao

Paul Marchal

Hendrik Fw Dekkers

Claude Desset

Marc Van Heijningen

Methods and apparatus for performing machine learning tasks, and in particular, to a neural-network-processing architecture and circuits for improved handling of partial accumulation results in weight-stationary operations, such as operations occurring in compute-in-memory (CIM) processing elements (PEs). One example PE circuit for machine learning generally includes an accumulator circuit, a flip-flop array having an input coupled to an output of the accumulator circuit, a write register, and a first multiplexer having a first input coupled to an output of the write register, having a second input coupled to an output of the flip-flop array, and having an output coupled to a first input of the first accumulator circuit.

Partial sum management and reconfigurable systolic flow architectures for in-memory computation

An integrated circuit includes a trench power rail to reduce resistance in a power rail or avoid an increase in resistance of a power rail as a result of the metal tracks being reduced in size as the technology node size is reduced. The trench power rail is formed in isolation regions between cell circuits. A cell isolation trench in the isolation region provides additional volume in which to dispose additional metal material for forming the trench power rail to increase its cross-sectional area. The trench power rail extends through a via layer to a metal layer, including signal interconnects. The trench power rail extends in a width direction out of the cell isolation trench in the via layer to couple to trench contacts of the adjacent cell circuits without vertical interconnect accesses (vias). A high-K dielectric layer can selectively isolate the trench power rail from the cell circuits.

Trench power rail in cell circuits to reduce resistance and related power distribution networks and fabrication methods

Certain aspects generally relate to performing machine learning tasks, and in particular, to computation-in-memory architectures and operations. One aspect provides a circuit for in-memory computation. The circuit generally includes multiple bit-lines, multiple word-lines, an array of compute-in-memory cells, and a plurality of accumulators, each accumulator being coupled to a respective one of the multiple bit-lines. Each compute-in-memory cell is coupled to one of the bit-lines and to one of the word-lines and is configured to store a weight bit of a neural network.

Digital compute in memory

Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM array circuits for multiple operations per column are disclosed. A DCIM bit cell array circuit including DCIM bit cell circuits comprising exemplary DCIM bit cell circuit layouts disposed in columns is configured to evaluate the results of multiple multiply operations per clock cycle. The DCIM bit cell circuits in the DCIM bit cell circuit layouts each couples to one of a plurality of column output lines in a column. In this regard, in each cycle of a system clock, each of the plurality of column output lines receives a result of a multiply operation of a DCIM bit cell circuit coupled to the column output line. The DCIM bit cell array circuit includes digital sense amplifiers coupled to each of the plurality of column output lines to reliably evaluate a result of a plurality of multiply operations per cycle.

Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM arrays for multiple operations per column

Aspects of the disclosure are directed to an integrated circuit. The integrated circuit may include a signaling interconnect having a narrow trench disposed within a metallization layer, and a power rail having a wide trench disposed within the metallization layer, wherein the signaling interconnect comprises non-copper material and the power rail comprises copper. The non-copper material may include at least one of ruthenium (Ru), tungsten (W), aluminum (Al), and cobalt (Co). The signaling interconnect and power rail may be processed in a common chemical mechanical polishing step and have approximately the same trench depth. A metal cap may be deposited on top of the power rail.

Hybrid metallization interconnects for power distribution and signaling

The disclosed technology generally relates to semiconductor devices and more particularly to a gate structure for a semiconductor device, and to methods of forming the same. In an aspect a method for forming a gate structure includes forming a first set of one or more semiconductor features and a second set of one or more semiconductor features. The method additionally includes forming a sacrificial gate extending across the semiconductor features of the first set and the semiconductor features of the second set. The method additionally includes forming a hole by etching the sacrificial gate, wherein the sacrificial gate is divided into a first sacrificial gate section and a second sacrificial gate section, forming a barrier in the hole by depositing a barrier material in the hole, removing the first sacrificial gate section and the second sacrificial gate section by etching wherein a first trench section is formed and a second trench section is formed, forming a first gate conductor in the first trench section and the second trench section, forming a mask above the second trench section, the mask exposing the first trench section, etching the first gate conductor in the first trench section, wherein the mask and the barrier counteracts etching of the first gate conductor in the second trench section, and forming a second gate conductor in the first trench section.

Method of forming gate of semiconductor device and semiconductor device having same

Integrated circuits employing a field gate(s) without dielectric layers and/or work function metal layers for reduced gate layout parasitic resistance, and related methods are disclosed. At least a portion of the dielectric layers and/or work function metal layers present in active gate(s) is not present in a field gate(s) of a gate in a circuit cell. The field gate(s) have more conductive gate material than the active gate(s). In this manner, the increased volume of gate material in the field gate(s) reduces gate layout parasitic resistance. The active gate(s) retains the dielectric layers and/or work function metal layers to effectively isolate the gate material from a channel of a FET formed from the circuit cell to provide effective channel control. Reducing gate layout parasitic resistance can reduce current (I) resistance (R) (IR) drop to achieve the desired drive strength in the integrated circuit.

Integrated circuits employing a field gate(s) without dielectric layers and/or work function metal layers for reduced gate layout parasitic resistance, and related methods

Integrating a gate-all-around (GAA) field-effect transistor(s) and a FinFET(s) on a common substrate of a semiconductor die is disclosed. GAA FETs and FinFETs can form integrated circuits (ICs). GAA FETs and FinFETs are integrated on a common substrate to optimize advantages of each type of FET. For example, FinFETs may be formed in the common substrate in the semiconductor die for forming circuits where reduced resistance and capacitance are important for performance, whereas GAA FETs may be formed in the common substrate in the semiconductor die for forming circuits with decreased threshold voltage to allow voltage scaling to lower supply voltages to reduce power consumption and also to reduce silicon area as a result of vertically stacked devices. This supports a designer having the freedom to separate control the channel width of the GAA FETs and FinFETs, which may be important for controlling drive strength and/or area for different circuits.

Integrating a gate-all-around (GAA) field-effect transistor(s) (FET(S)) and a finFET(s) on a common substrate of a semiconductor die

Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop are disclosed. In one aspect, a standard cell circuit is provided that employs active devices that include corresponding gates disposed with a gate pitch. First and second voltage rails having a line width are disposed in a first metal layer. Employing the first and second voltage rails having substantially a same line width reduces the height of the standard cell circuit as compared to conventional standard cell circuits. Metal lines are disposed in a second metal layer with a metal pitch less than the gate pitch such that the number of metal lines exceeds the number of gates. Electrically coupling the first and second voltage rails to the metal shunts increases the conductive area of each voltage rail, which reduces a voltage drop across each voltage rail.

Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop

A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.

Nanowire device with reduced parasitics

Selectively recessing trench isolation in three-dimensional (3D) transistors to vary channel structure exposures from trench isolation to control drive strength is disclosed. The ability to vary the exposures of channel structures in 3D transistors from trench isolation allows the drive strengths of the 3D transistors to be varied. Varying the drive strengths of 3D transistors may be advantageous in certain circuit applications to reduce power consumption and/or control drive strength ratios between transistors, as examples. In this regard, in exemplary aspects disclosed herein, during the fabrication of 3D transistors, a trench isolation material is disposed adjacent to channel structures formed from a substrate. The amount of trench isolation material disposed adjacent to each channel structure determines the amount of channel structure surface area exposed to a gate. The amount of channel structure surface area of the 3D transistor exposed to the gate affects the drive strength of the 3D transistor.

Selectively recessing trench isolation in three-dimensional (3D) transistors to vary channel structure exposures from trench isolation to control drive strength

Standard cell circuits employing high aspect ratio voltage rails for reduced resistance are disclosed. In one aspect, a standard cell circuit is provided that employs a first high aspect ratio voltage rail configured to receive a first supply voltage. A second high aspect ratio voltage rail is employed that is disposed substantially parallel to the first high aspect ratio voltage rail. A voltage differential between the first and second high aspect ratio voltage rails is used to power a circuit device in the standard cell circuit. The first and second high aspect ratio voltage rails each have a height-to-width ratio greater than 1.0. The height of each respective first and second high aspect ratio voltage rail is greater than each respective width. Employing the first and second high aspect ratio voltage rails allows each to have a cross-sectional area that limits the resistance and corresponding IR drop.

Standard cell circuits employing high aspect ratio voltage rails for reduced resistance

A method includes forming a first spacer structure on a dummy gate of a semiconductor device and forming a sacrificial spacer on the first spacer structure. The method also includes etching a structure of the semiconductor device to create an opening, removing the sacrificial spacer via the opening, and depositing a material to close to define a gap.

Semiconductor device having a gap defined therein

A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.

Vertically stacked nanowire field effect transistors

Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices are disclosed. In one aspect, an exemplary CMOS device includes a nanowire channel structure that includes a plurality of continuously stacked nanowires. Vertically adjacent nanowires are connected at narrow top and bottom end portions of each nanowire. Thus, the nanowire channel structure comprises a plurality of narrow portions that are narrower than a corresponding plurality of central portions. A wrap-around gate material is disposed around the nanowire channel structure, including the plurality of narrow portions, without entirely wrapping around any nanowire therein. The exemplary CMOS device provides, for example, a larger effective channel width and better gate control than a conventional fin field-effect transistor (FET) (FinFET) of a similar footprint. The exemplary CMOS device further provides, for example, a shorter nanowire channel structure than a conventional nanowire FET.

Growing community of inventors

Leuven, Belgium

Mustafa Badaroglu