Efficient Power Conversion Corporation

Muskan Sharma

Jianjun Cao

Fang Chang Liu

Yoganand Saripalli

Jie Hu

Wen-Chia Liao

Gordon Stecklein

An integrated circuit which includes a GaN FET and a metal-insulator-metal capacitor. The capacitor is fully integrated with a lateral GaN process flow, i.e., the same gate metal layer, field plate metal layer and dielectric layer of the GaN FET are also used to form the bottom plate, insulator and top plate of the capacitor. The top plate is contacted by a conductive via, which extends through the top plate. To increase the voltage breakdown capability of the capacitor of the integrated circuit, a portion of the gate metal layer is formed in the shape of a ring around the conductive via.

Gate metal-insulator-field plate metal integrated circuit capacitor and method of forming the same

A gallium nitride (GaN) transistor which includes multiple insulator semiconductor interface regions. Two or more first insulator segments and two or more second insulator segments are positioned between the gate and drain contacts and interleaved together. At least one first insulator segment is nearer to the gate contact than the second insulator segments. At least one second insulator segment is nearer to the drain contact than the first insulator segments. The first and second insulators are chosen such that a net electron donor density above the channel under the first insulator segments is lower than a net electron density above the channel under the second insulator segments. The first insulator segments reduce gate leakage and electric fields near the gate that cause high gate-drain charge. The second insulator segments reduce electric fields near the drain contact and provide a high density of charge in the channel for reduced on-resistance.

Field plate structures with patterned surface passivation layers and methods for manufacturing thereof

A lateral power semiconductor device with a metal interconnect layout for low on-resistance. The metal interconnect layout includes first, second, and third metal layers, each of which include source bars and drain bars. Source bars in the first, second, and third metal layers are electrically connected. Drain bars in the first, second, and third metal layers are electrically connected. In one embodiment, the first and second metal layers are parallel, and the third metal layer is perpendicular to the first and second metal layers. In another embodiment, the first and third metal layer are parallel, and the second metal layer is perpendicular to the first and third metal layers. A nonconductive layer ensures solder bumps electrically connect to only source bars or only drain bars. As a result, a plurality of available pathways exists and enables current to take any of the plurality of available pathways.

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Torrance, CA, United States of America

Muskan Sharma