Infineon Technologies Ag

Siemens Aktiengesellschaft

Musa Saglam

Stefan Dietrich

Michael Markert

Thomas Hein

Alessandro Minzoni

Patrick Heyne

Christian Weis

Thilo Marx

Peter Schr&ouml;gmeier

Sabine Sch&ouml;niger

Peter Schrogmeier

Sabine Schoniger

Rao Rajashekhar

A clock signal synchronization method and an apparatus device for utilization with the synchronization of clock signals is disclosed. In one embodiment the apparatus includes a delay device with a variably controllable delay time into which a clock signal, or a signal obtained therefrom, is input, charged with the variably controllable delay time, and output as a delayed clock signal. A device is provided for determining whether a clock edge of the delayed clock signal output by the delay device, or of a signal obtained therefrom, lies within a predetermined time window before a corresponding clock edge of the clock signal, or of the signal obtained therefrom.

Device for utilization with the synchronization of clock signals, and clock signal synchronizing method

A delay device has series-connected multiplexers in a differential form. First connections of the multiplexers are connected to the output of an upstream multiplexer. Second inputs of the multiplexers are connected to the input connection to which the signal to be delayed can be supplied. A control signal controls the switch setting of one of the multiplexers such that its output is connected to the input of the delay device. The other multiplexers have the other switch setting. In consequence, a specific delay time is set for the delay device. The multiplexers have four current paths which are coupled in pairs. One of the current path pairs can be decoupled from the current source via a transistor.

Integratable, controllable delay device, use of a delay device, as well as an integratable multiplexer for use in a delay device

The integrated memory has a first address path, via which the address terminals are connected to first selection lines of a first group and which has corresponding first lines and a first decoder circuit. In addition, the integrated memory has a second address path, via which the address terminals are connected to first selection lines of a second group and which has corresponding second lines and a second decoder circuit. The first decoder circuit is faster than the second decoder circuit. The first lines have a longer signal propagation time than the second lines.

Integrated memory

In a semiconductor memory, bit lines are disposed in such a way that in each case two inverted and two non-inverted bit lines lie next to one another. Adjacent switching transistors for connecting the bit lines to an inverted or a non-inverted collective line are connected to the corresponding collective line by a common contact. An advantage in terms of area is afforded by the fact that the two switching transistors have a common doping region.

Semiconductor memory having differential bit lines

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Munich, Germany

Musa Saglam