Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Murugasamy K Nachimuthu

Mohan J Kumar

Dimitrios Ziakas

Mahesh S Natu

Susanne M Balle

Francesc Guim Bernat

Sarathy Jayakumar

Daniel Rivas Barragan

Rahul Khanna

Suraj Prabhakaran

Slawomir Putyrski

Sergiu D Ghetie

Mark A Schmisseur

Bill Nale

Jose Andy Vargas

Alberto J Munoz

Jun Zhu

Robert Charles Swanson

Rajat Agarwal

George Vergis

Vincent J Zimmer

Michael A Rothman

Debendra Das Sharma

Srinivas Chennupaty

Akhilesh Kumar

Narayan Ranganathan

Theodros Yigzaw

Phanindra Mannava

Kuljit Singh Bains

Karthik Kumar

Rajesh M Sankaran

Sujoy Sen

Raj K Ramanujan

Koichi Yamada

Michael T Crocker

Ioannis T Schoinas

James B Crossland

Ashok Raj

Aaron Gorius

Richard Paul Mangold

Jiewen Yao

Vasudevan Srinivasan

Allen Jay Baum

Cong Li

Jian Tang

John V Lovelace

John Chun Kwok Leung

Neeraj S Upasani

Shamanna M Datta

Yufu Li

Anil S Keshavamurthy

Camille C Raad

Wojciech S Powiertowski

Xiaohua Cai

Krishna Bhuyan

Jeanne Guillory

Tuan M Quach

Mani Ayyar

Robert A Branch

Sagar V Dalvi

Andy M Rudoff

Chukwunenye S Nnebe

Scott W Kirvan

Sundar Muthusamy

Suresh K Marisetty

Bassam N Coury

Muthukumar Swaminathan

Doddaballapur N Jayasimha

Baskaran Ganesan

Anjaneya Reddy Chagam Reddy

Debaleena Das

Scott David Peterson

Mark S Myers

Muralidharan Sundararajan

Mariusz Oriol

Jonathan C Jasper

Xiaoming Du

Gautam Doshi

Brett P Wang

Mrittika Ganguli

Russell J Wunderlich

Deepak Gandiga Shivakumar

Thi Dang

Dan J Williams

Ronald N Story

Daniel K Osawa

Tiffany J Kasanicky

Shen Zhou

Ruixia Li

Maciej Plucinski

Jim B Crossland

Stan Domen

Siyuan Fu

Rajender Kuramkote

Doddabaliapur Narasimha-Murthy Jayasimha

Koo Heng Daniel Aw

Wenson Lin

Singaravelan Nallasellan

Maciej Lawniczak

Chao Yan Tang

A system can predict memory device failure through identification of correctable error patterns based on the memory architecture. The failure prediction can thus account for the circuit-level of the memory rather than the mere number or frequency of correctable errors. A failure prediction engine correlates hardware configuration of the memory device with correctable errors (CEs) detected in data of the memory device to predict an uncorrectable error (UE) based on the correlation.

Uncorrectable memory error prediction

Methods, apparatus, systems, and articles of manufacture to perform a pseudo-S3 protocol to update firmware and/or activate new firmware with a warm reset are disclosed. An example apparatus includes an advanced configuration and power interface (ACPI) to: initiate a pseudo-sleep event in response to identifying a firmware update; and assert a power button event, the power button event to cause an operating system (OS) to prepare to enter into a sleep state; a basic input/output system (BIOS) to: initiate a warm reset in response to the OS preparing to enter the sleep state, the warm reset to update firmware according to the firmware update; and transmit a wake vector to the OS to continue operation.

Methods and apparatus to perform a pseudo-S3 protocol to update firmware and/or activate new firmware with a warm reset

Methods and apparatus for seamless SMM (System Management Mode) global driver update base on SMM Root-of-Trust. Mechanisms are provided to load and replace SMM drivers at runtime in a secure manner, without requiring an SMM firmware update and platform reset. SMM code is executed by BIOS during boot in a hidden area of memory called SMRAM space. Seamless update using an SMM Global Driver Update provides a method to load and replace all SMM drivers (including SMM infrastructure) on an already shipped platform production for purposes such as bug fixes. The principles and teachings may also be applied to update other types of secure execution mode code in addition to SMM code.

Seamless SMM global driver update base on SMM root of trust

Embodiments are generally directed apparatuses, methods, techniques and so forth determine an access level of operation based on an indication received via one or more network links from a pod management controller, and enable or disable a firmware update capability for a firmware device based on the access level of operation, the firmware update capability to change firmware for the firmware device. Embodiments may also include determining one or more configuration settings of a plurality of configuration settings to enable for configuration based on the access level of operation, and enable configuration of the one or more configuration settings.

Techniques to control system updates and configuration changes via the cloud

Technologies for providing latency-aware consensus management in a disaggregated system include a compute device. The compute device includes circuitry to determine latencies associated with subsystems of the disaggregated system. Additionally, the circuitry is to determine, as a function of the determined latencies, a time period in which a configuration change to the disaggregated system is to reach a consistent state in the subsystems.

Technologies for providing latency-aware consensus management in a disaggregated architecture

Examples described herein provide a central processing unit (CPU) to reserve a region of memory for use to store both a boot firmware code and a second boot firmware code and to perform the second boot firmware code without reboot. The reserved region of memory can be a region that is not configured for access by an operating system (OS). The reserved region of memory comprises System Management Random Access Memory (SMRAM). If a first interrupt handler is not overwritten after a second boot firmware code is stored, the CPU can roll back to use of the first interrupt handler.

Update of boot code handlers

Technologies for composing a managed node with multiple processors on multiple compute sleds to cooperatively execute a workload include a memory, one or more processors connected to the memory, and an accelerator. The accelerator further includes a coherence logic unit that is configured to receive a node configuration request to execute a workload. The node configuration request identifies the compute sled and a second compute sled to be included in a managed node. The coherence logic unit is further configured to modify a portion of local working data associated with the workload on the compute sled in the memory with the one or more processors of the compute sled, determine coherence data indicative of the modification made by the one or more processors of the compute sled to the local working data in the memory, and send the coherence data to the second compute sled of the managed node.

Cloud-based scale-up system composition

Examples include updating firmware for a persistent memory module in a computing system during runtime. Examples include copying a new version of persistent memory module firmware into an available area of random-access memory (RAM) in the persistent memory module, and transferring processing of a current version of persistent memory module firmware to the new version of persistent memory module firmware during runtime of the computing system, without a reset of the computing system and without quiesce of access to persistent memory media in the persistent memory module, while continuing to perform critical event handling by the current version of persistent memory module firmware. Examples further include initializing the new version of persistent memory module firmware; and transferring processing of critical event handling from the current version of persistent memory module firmware to the new version of persistent memory module firmware when initializing the new version of persistent memory module firmware is completed.

Memory device firmware update and activation without memory access quiescence

Technologies for fast boot-up of a compute device with error-correcting code (ECC) memory are disclosed. A basic input/output system (BIOS) of a compute device may assign memory addresses of the ECC memory to different processors on the compute device. The processors may then initialize the ECC memory in parallel by writing to the ECC memory. The processors may write to the ECC memory with direct-store operations that are immediately written to the ECC memory instead of being cached. The BIOS may continue to operation on one processor while the rest of the processors initialize the ECC memory.

Technologies for fast booting with error-correcting code memory

Systems, apparatuses and methods may provide for technology that exchanges activation information between system firmware and an operating system (OS), wherein the activation information includes one or more of status information, activation state information, capability information, activation time information or quiesce time information. The technology also conducts a runtime upgrade of the device firmware based on the activation information, wherein the runtime upgrade bypasses a reboot of the computing system.

Interface and warm reset path for memory device firmware upgrades

Embodiments are generally directed apparatuses, methods, techniques and so forth to receive a sled manifest comprising identifiers for physical resources of a sled, receive results of an authentication and validation operations performed to authenticate and validate the physical resources of the sled, determine whether the results of the authentication and validation operations indicate the physical resources are authenticate or not authenticate. Further and in response to the determination that the results indicate the physical resources are authenticated, permit the physical resources to process a workload, and in response to the determination that the results indicate the physical resources are not authenticated, prevent the physical resources from processing the workload.

Techniques to verify and authenticate resources in a data center computer environment

Mechanisms for out-of-band (OOB) management of Field Programmable Gate Array (FPGA) bitstreams and associated methods, apparatus, systems and firmware. Under a first OOB mechanism, a management component, such as a baseband management controller (BMC) is coupled to a processor including an agent in a compute node that includes an FGPA. An FPGA bitstream file is provided to the BMC, and the agent reads the file from the BMC and streams the FPGA bitstream contents in the file to the FPGA to program it. Under second and third OOB mechanisms, a pointer to an FPGA bitstream file that identifies the location of the file that is accessible via a network or fabric is provided to the BMC or other management entity. The BMC/management entity forwards the pointer to BIOS running on the compute node or an agent on the processor. The BIOS or agent then uses the pointer to retrieve the FPGA bitstream file via the network or fabric, as applicable, and streams the FPGA bitstream to the FPGA to program it.

Out-of-band management of FPGA bitstreams

Technologies for providing efficient pooling for a system that includes a hyper converged infrastructure. A sled of the system includes a network interface controller that includes a first bridge logic unit to communicatively couple to a network of bridge logic units. The first bridge logic unit is further to obtain, from a requestor device, a request to access a requested device, determine whether the requested device is on the present sled or on a remote sled different from the present sled, selectively power on, in response to a determination that the requested device is located on the present sled, the requested device, communicate, in response to a determination that the requested device is on the remote sled, with a second bridge logic unit of the remote sled, and provide, to the requestor device through the first bridge logic unit, access to the requested device.

Technologies for providing efficient pooling for a hyper converged infrastructure

Embodiments are generally directed apparatuses, methods, techniques and so forth to select two or more processing units of the plurality of processing units to process a workload, and configure a circuit switch to link the two or more processing units to process the workload, the two or more processing units each linked to each other via paths of communication and the circuit switch.

Techniques to configure physical compute resources for workloads via circuit switching

Growing community of inventors

Beaverton, OR, United States of America

Murugasamy K Nachimuthu