Ncr Corporation

Murray L Trudel

George C Lockwood

Robert F Pfeifer

John K Stewart, Jr

Michael R Gulett

Edward H Honnigford

Vinod K Dham

G Glenn Evans

A process for fabricating volatile and nonvolatile field effect devices on a common semiconductor wafer, and a unique composite structure for a nonvolatile memory device fabricated according to the process. A distinct feature of the process is the elimination of nitride from beneath any poly I layers while selectively retaining sandwiched and coextensive segments of nitride and poly II layers for the memory devices. In one form, the method commences with a wafer treated according to the general localized oxidation of silicon process, followed by a blanket enhancement implant and selectively masked depletion implants. The succeeding contact etch step is followed by a deposition of a poly I layer, a resistor forming implant and a patterned etch of the poly I layer. Thereafter, a first isolation oxide is grown, selective implants are performed to center the memory window, the memory area is etched, and the memory area is covered by a regrowth of a very thin memory oxide. The wafer is then coated with nitride and poly II, before undergoing a patterned plasma etch which successively and coextensively removes poly II and nitride in unwanted areas. Consequently, any nitride which remains is in a sandwiched arrangement with an overlying layer of poly II. The process inherently retains no nitride under any poly I layer, and thereby enhances the reliability of the complete IC. The composite nonvolatile memory device includes a poly II nonvolatile memory capacitor, a poly II depletion IGFET, and a poly I depletion IGFET over a single continuum of channel. The structural arrangement provides for selective access to the nonvolatile memory capacitor through the poly I IGFET during the write mode.

Mixed dielectric process and nonvolatile memory device fabricated thereby

Disclosed is a process for a CMOS integrated circuit having polysilicon conductors of a single conductivity, single impurity type. After forming the conductors they are covered by an oxidation and diffusion mask consisting of a dual layer of silicon dioxide and silicon nitride. Then, source and drains of the p-channel and n-channel transistors are formed. Next, an implantation or diffusion barrier is grown over sources and drains. The oxidation and diffusion mask over all the conductors is then removed and they are all doped simultaneously using a single type impurity. The process may be used to additionally form polysilicon resistors by initially doping the polysilicon to a low level of conductivity. After forming the conductors and resistors they are covered by the oxidation and diffusion mask. Then a resistor mask of either silicon nitride or polysilicon is formed over the resistors to protect them during the high conductivity doping of the conductors.

Method for fabricating improved complementary metal oxide semiconductor

A three gate programmable memory cell comprised of a variable threshold memory element medial of two access gate elements, together forming a series path whose conductive state can be altered by any one of the series elements. Each cell has lines for individually accessing the three gate electrodes, in addition to line connections to opposite ends of the conductive path formed by the elements in series. In one form, an alterable threshold transistor is connected in series between two field effect transistors, one of the two controlling cell addressing and the other actuating the read mode. The cell is erased with a high voltage pulse on the memory line. Subsequent programming of the cell is defined by the voltage states on the word and bit lines of the addressing transistor in time coincidence with an opposite polarity, shorter duration pulse on the memory line. The logic state stored in the cell is defined by the presence or absence of a conductive path through the cell when all three gates are biased to their read mode levels. A unitary configuration of the cell includes a single substrate, with a channel defined between doped node regions. Electrically isolated gate electrodes of the three transistors are symmetrically disposed adjacent each other over the channel to control its conductivity in segments. The cells are amenable to being grouped in arrays, while retaining the independence of the high voltage memory line and the flexibility of individual row and column addresses.

Earom cell matrix and logic arrays with common memory gate

A low voltage write, avalanche breakdown, nonvolatile MNOSFET memory device. The device is preferably an n-channel enhancement mode, split-gate or trigate structure having a first, relatively highly doped p+ channel region and a second, underlying p-region. The p+ region is coextensive with the thin, memory oxide structure. The binary state of the device is selected by applying a low voltage (e.g., +12v) to the gate and simultaneously applying a suitable voltage to the source and/or drain to induce avalanche breakdown in the channel, or not, to write the device to a '1' state or maintain the device in its original '0' state.

Low voltage nonvolatile memory device

A method of conditioning a nitride surface by treating it with ionized oxygen is disclosed. The nitride surface is placed in a vacuum and treated with the ionized oxygen for a period of time sufficient to condition the nitride for subsequent processing steps. The ionized oxygen treatment is performed substantially at ambient temperature. The conditioning method is included in a process for improving the adhesion characteristics of a photoresist film to a silicon nitride surface. A liquid solution of hexamethyldisilazane is applied to the conditioned nitride surface. Thereafter, a photoresist is applied, exposed through a photographic mask and developed in a known manner for the purpose of forming a photoresist masking film pattern. The photoresist film pattern typically serves as a mask during an etching process in which areas not covered by photoresist are removed by a suitable etching solution.

Method for conditioning nitride surface

A process for forming polysilicon-to-substrate contacts. The process permits the use of a polysilicon-to-substrate contact mask and eliminates the exposure of the substrate in the contact regions to the polysilicon etch. The polysilicon contact-forming conductors are formed from a layer of polysilicon by etching partially through the layer to leave a residual layer surrounding and defining the conductors; converting the residual polysilicon to oxide; and selectively etching the oxide. The result is a damage-free substrate contact region exhibiting reduced junction leakage current.

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Centerville, OH, United States of America

Murray L Trudel