Micron Technology Incorporated

Sandisk Technologies Inc.

Murong Lang

Zhenming Zhou

Zhongguang Xu

Tingjun Xie

Li-Te Chang

Zhenlei Shen

Jiangli Zhu

Jian Huang

Ching-Huang Lu

Mikai Chen

Peng Zhang

Yu-Chung Lien

Fangfang Zhu

Charles See Yeung Kwong

Nagendra Prasad Ganesh Rao

Deepanshu Dutta

Seungjune Jeon

Wei Wang

Christina Papagianni

Lei Lin

Vamsi Pavan Rayaprolu

Zhengang Chen

Ting Luo

Ugo Russo

Niccolo' Righetti

Nicola Ciocchini

Frederick Adi

Ronit Roneel Prakash

Michael G Miller

Cynthia Hsu

Pitamber Shukla

Charles S Kwong

Sead Zildzic, Jr

Sead Zildzic

Aaron Lee

Hanping Chen

A processing device in a memory sub-system determines one or more read margin levels associated with the memory device. A machine learning model is applied to the one or more read margin levels to generate a read margin prediction value associated with the memory device. Based on the margin prediction value, the memory device is assigned to a selected bin of a set of bins. A media scan operation is executed on the memory device in accordance with a scan frequency associated with the selected bin.

Adaptive scanning of memory devices with supervised learning

Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive read level threshold voltage operations. The controller determines a first read level offset associated with reading a first set of data from a first level using a first read level of a plurality of read levels. The controller applies the first read level offset to a machine learning model to estimate a second read level offset, associated with reading a second set of data from a second level of the plurality of levels, using a second read level of the plurality of read levels. The controller updates, based on the first read level offset and the estimated second read level offset, a look-up table that includes a set of read level offsets used to read data from the plurality of levels of the individual component.

Model based error avoidance

An example includes a method for performing a block family (BF) scan operation of a memory device. The method includes performing a first block family error avoidance (BFEA) scan via a controller on a wordline of a first fractional good block of a virtual block. The method also includes performing a second BFEA scan via the controller on a wordline of a second fractional good block of the virtual block. The method also includes determining a BF bin number for each of the first and second fractional good blocks via the controller based on the first and second BFEA scans. The method further includes refreshing data stored in the virtual block via the controller based on the respective BF bin numbers of the first and second fractional good blocks.

Block family management for a virtual block

In some implementations, a memory device may determine that a power loss has occurred. The memory device may determine a last written page (LWP) location associated with an LWP of a block of a memory of the memory device. The memory device may determine one of: a word line group (WLG) associated with the LWP location and at least one WLG-dependent offset associated with the WLG, or a partial block (PB) fill ratio associated with the LWP location and at least one PB-fill-ratio-dependent offset associated with the PB fill ratio. The memory device may perform a power loss error detection procedure based on one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset by applying the one of the at least one WLG-dependent offset or the at least one PB-fill-ratio offset to at least one read reference voltage.

Power loss error detection using partial block handling

Methods, apparatuses and systems related to managing read levels across multiple groupings or decks are described. The apparatus may include a read level management mechanism configured to controls or dynamically adjusts the read levels for the different groupings according to a real-time condition/measure associated with the programming delays.

Apparatus with multi-deck read level management and methods for operating the same

Methods, systems, and apparatuses include moving a portion of memory to a garbage pool in response to determining that the portion of memory is invalid. The portion of memory is erased in response to determining that the portion of memory is invalid. A request to move an additional portion of memory to a free pool from the garbage pool is received. A free pool includes a queue including erased portions of memory, which serve as next portions of memory to fulfill subsequent cursor requests. The erased portion of memory is moved from the garbage pool to the free pool.

Optimizing data reliability using erase retention

A block of a memory device is identified. A threshold voltage offset corresponding to a wordline associated with the block is identified based on a threshold voltage offset table. The threshold voltage offset table corresponds to at least one of: a value of a media state metric associated with the block, a wordline group of the wordline, or a difference between the wordline and a boundary wordline of the block. A read operations is performed on the block using a read level voltage modified by the threshold voltage offset, wherein the read level voltage is associated with the block.

Error avoidance for partially programmed blocks of a memory device

A processing device in a memory sub-system logically closes a block of a memory device to prevent additional program operations from being performed on the block. The processing device further causes one or more wordlines of the block to be programmed with padding data. The one or more wordlines are adjacent to a last wordline of the block programmed before the block was logically closed. In addition, the processing device causes a remaining set of wordlines of the block to be concurrently programmed to a single program state.

Partial block handling protocol in a non-volatile memory device

A system includes a memory device with multiple cells and a processing device to perform operations including: identifying a group of wordlines, each connected to a subset of cells, and assigning a specified charge loss classification value to that group. The operations can also include selecting a page level, selecting a first set of cells, determining, for the first set of cells, a value of a first data state metric, identifying a second set of cells charged to a specified charge state, and determining a value of a second data state metric. The operations can also include maintaining a skew counter of the second data state metric, identifying and updating a read reference voltage offset, as well as applying the updated read reference voltage offset in a read operation.

Dynamic read calibration

Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A sensing time is determined using the cycle number and the group. The command is executed using the sensing time.

Adaptive sensing time for memory operations

A processing device in a memory sub-system detects an occurrence of a data integrity check trigger event in the memory sub-system, and in response, identifies a memory die of a plurality of memory dies in the memory sub-system. The processing device further determines a read margin associated with a first distribution of memory cells of the identified memory die, and determines an adaptive scan frequency for the identified memory die based on the read margin associated with the first distribution of memory cells.

Adaptive integrity scan in a memory sub-system

A memory device can include a memory device coupled with a processing device. The processing device causes a first erase operation to be performed at a block, where the first erase operation causes a pre-program voltage and a first erase voltage having a first magnitude to be applied to the block. The processing device causes an erase detection operation to be performed at the block. The processing device determines that the block fails to satisfy the erase detection operation responsive to causing the erase detection operation to be performed. The processing device further causes a second erase operation to be performed at the block responsive to determining that the block failed the erase detection operation, where the second erase operation causes a second erase voltage having a second magnitude to be applied to the block.

Low stress refresh erase in a memory device

A method for receiving a request for performing a programming operation on one or more memory blocks of a memory device, identifying a value of a media endurance metric associated with the one or more memory blocks, determining a programming voltage offset corresponding to the value of the media endurance metric, and performing, using the programming voltage offset, the programming operation on the one or more memory blocks. The method further includes identifying a program-verify voltage level associated with the one or more memory blocks, determining a program-verify voltage offset associated with the program-verify voltage level and the value of the media endurance metric, and performing, using the program-verify voltage level and the program-verify voltage offset, a program-verify operation on the one or more memory blocks.

Modification of program voltage level with read or program-verify adjustment for improving reliability in memory devices

Aspects of the present disclosure configure a system component, such as memory sub-system controller, to perform empty page scan operations. The controller selects a portion of the set of memory components that is empty and ready to be programmed. The controller reads one or more signals from the selected portion of the set of memory components. The controller generates an error count value representing whether the portion of the set of memory components is valid for programming based on a result of reading the one or more signals from the selected portion. The controller updates a scan frequency for performing the empty page scan operations for the portion of the set of memory components based on the error count value.

Empty page scan operations adjustment

A threshold criterion of a plurality of threshold criteria is identified based on a current program-erase cycle (PEC) count of a first block of a memory device, wherein the first block is configured as quad-level cell (QLC) memory. A raw bit error rate (RBER) associated with data of a second block of the memory device is determined, wherein the second block is configured as single-level cell (SLC) memory. It is determined that the RBER associated with the data of the second block satisfies the threshold criterion. In response to determining that the RBER satisfies the threshold criterion, the data of the second block is written to the first block.

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San Jose, CA, United States of America

Murong Lang