Intel Corporation

Cirrus Logic Inc.

Marvell International Limited

Murli Ganeshan

Nigel C Paver

Bradley C Aldrich

Wing K Yu

Gregory Allen North

Mark Norman Fullerton

Stephen J Strazdus

Mukesh Patel

Rupal Parikh

William T Maghielse

Jianwei Liu

Anthony Jebson

Deli Deng

Kailesh B Bavaria

According to some embodiments, a technique provides for the execution of an instruction that includes receiving residual data of a first image and decoded pixels of a second image, zero-extending a plurality of unsigned data operands of the decoded pixels producing a plurality of unpacked data operands, adding a plurality of signed data operands of the residual data to the plurality of unpacked data operands producing a plurality of signed results; and saturating the plurality of signed results producing a plurality of unsigned results.

Residual addition for video software techniques

A math coprocessorincludes a multiply-accumulate unit. Multiplier-accumulate unitincludes a multiplier arrayfor selectively multiplying first and second operands, the first and second operands having a data type selected from the group including floating point and integer data types. An adderselectively performs addition and subtraction operations on third and fourth operands, the third and fourth operands selected by multiplexer circuitry from the contents of a set of associated source registers, data output from multiplier arrayand data output from adder

Math coprocessor

A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a coprocessor targetted by the coprocessor instructions. After determining whether to alternatively load source values into a respective one of two source registers, new source values are transferred to one or more of the source registers. The coprocessor executes the coprocessor instruction, which includes an offset information, to extract values from the source registers based on the offset information and places the values in a destination register.

Extracting aligned data from two source registers without shifting by executing coprocessor instruction with mode bit for deriving offset from immediate or register

A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type. A source register in the main processor and a destination register is in the coprocessor, those registers including data elements. The coprocessor instruction includes an opcode specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for the coprocessor instruction, the instruction to broadcast a data element from said source register to said destination register.

Coprocessor processing instruction with coprocessor ID to broadcast main processor register data element to coprocessor multi-element register

A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.

Conditional execution of coprocessor instruction based on main processor arithmetic flags

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Austin, TX, United States of America

Murli Ganeshan