Ansys, Inc.

Gear Design Solutions

Murat Becer

John Lee

Altan Odabasi

Scott Johnson

Lei Yin

William Alan Mullen

Mustafa Yazgan

Aveek Sarkar

A chip package system comprising N multiple processor cores can be tested by receiving a data file characterizing the chip package system. Thereafter, simulation testing is conducted for each core for each of Mstates using the data file such that each core is active in each state while all other cores are inactive. Each simulation test results in a simulation. The simulations are then combined to result in a composite test covering Mcombinations. Related apparatus, systems, techniques and articles are also described.

Integrated circuit composite test generation

Described herein are systems and methods for a partitioned extraction-simulation technique that efficiently combines a partitioned extraction technique and a partitioned simulation technique by removing and not performing particular steps of the techniques to provide a more efficient netlist extraction and circuit simulation process. In some embodiments, a plurality of circuit simulators directly receive and process a plurality of sub-region netlists that are based on a spatial partitioning of the IC layout. In further embodiments, an EDA hybrid cloud system is implemented using pipelining and serializing of memory data. In these embodiments, an overall EDA process is divided into a plurality of pipelined stages to accelerate the computational speed of the overall EDA process. In further embodiments, EDA data is transferred, over a network, from a memory of one computer system directly to a memory of another computer system by serializing the EDA data.

System and method for netlist extraction and circuit simulation

System and method for hybrid cloud computing for electronic design automation

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Santa Clara, CA, United States of America

Murat Becer