Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Muralitharan Jayaraman

Narendhiran Chinnaanangur Ravimohan

Balakumar Rajendran

Abhijeet Manohar

Narendhiran Cr

Ramanathan Muthiah

Ramkumar Ramamurthy

Arun Thandapani

Vithya Kannappan

Sivaraj Velusamy

Abhinand Amarnath

Rohit Sathyanarayan

Satya Kesav Gundabathula

Indu Kumari

Idan Alrod

Alan David Bennett

Vijay Sivasankaran

Ankur Agrawal

Eyal Widder

Krishnamurthy Dhakshinamurthy

Chittoor Devarajan Sunilkumar

Chandra Lakkimsetty

Satrajit Chakraborty

Narendhiran Chinaaanangur Ravimohan

Mayur Jain

Garvita Chauhan

Prashantha Krishna

A storage device executes an adaptive flash interface module (FIM) protocol to optimize power consumption. The storage device includes a memory device including sets of dies and a set of FIMs. A FIM connects a controller to a set of dies on the memory device. The controller determines the mode of operation of the storage device and initializes the storage device in a first operating mode or a second operating mode. The controller makes at least one FIM non-operational when operating in the second operating mode and uses an operational FIM to communicate with multiple sets of dies on the memory device. The controller also makes a given number of FIMs operational when operating in the first operating mode and uses the operational FIM to communicate with a set of dies on the memory device. Operational FIMs accommodate a data rate for the mode of operation of the storage device.

Dynamic flash interface module (FIM) optimization

Aspects of a storage device are provided for efficient handling of logical metablock formation based on a heat distribution within the storage device. The storage device includes a plurality of memory dies each including a physical block, and a controller which forms a logical metablock from the physical blocks based on a location of each of the memory dies with respect to the controller. The controller stores a mapping of heat credit points to each of the physical blocks, where each of the heat credit points are associated with a respective heat level. The controller forms logical metablocks from the physical blocks based on the mapping. For instance, the controller forms different logical metablocks from physical blocks based on respective heat levels associated with memory dies including those blocks. As a result, efficient logical block formation may be achieved without significant complexity in firmware implementation.

Die location based logical block formation and handling

A storage system with privacy-centric multi-partitions and method for use therewith are provided. In one embodiment, a storage system comprises a memory configured to be partitioned into a plurality of partitions, wherein each partition is associated with its own boot block, and wherein each boot block is configured to boot any of the plurality of partitions. The storage system also comprises a controller configured to communicate with the memory and to: in response to a failure to boot one of the plurality of partitions with that partition's boot block, use a boot block of another one of the plurality of partitions to boot the one of the plurality of partitions; and restrict access to each of the plurality of partitions only to authenticated entities. Other embodiments are provided.

Storage system with privacy-centric multi-partitions and method for use therewith

Systems and methods are disclosed for a self-indexing removable storage device. In certain embodiments, the removable storage device is configured to be connected to a memory reader of a host device. The removable storage device comprises storage media, a controller configured to run firmware, and a buffer. The controller is configured to, while connected to a first host device, receive a write operation from the first host device, monitor changes to the storage media caused by the write operation, and update a file index stored on the removable storage device with the monitored changes. The controller is further configured to, in response to connecting the removable storage device to a memory reader of a second host device, provide the file index to an application on the second host device, and cause the application to display files on the storage media based on the file index.

Offloading file-indexing to memory card firmware

A method for error correction in a memory system includes determining a bit error ratio for a memory block of the memory system during a read operation. The method further includes determining whether the bit error ratio is between a first threshold and a second threshold. The method further includes based on a determination that the bit error ratio is between the first threshold and the second threshold, performing a select gate drain (SGD) read operation on a SGD word line of the memory block. The method further includes generating first soft bit data using SGD data corresponding to the SGD read operation. The method further includes performing a low-density parity-check correction using the first soft bit data on the memory block.

Failure mode study based error correction

Apparatuses and techniques are described for more efficiently allocating blocks of data in a memory device. The number of dedicated single-level cell (SLC) blocks which are allocated at the time of manufacture of a memory device can be reduced by transitioning a portion of the multi-level cell (MLC) blocks to an SLC mode at various times in the lifetime of the memory device. In one approach, separate counts are maintained for an MLC block in the SLC and MLC modes. The separate counts can be used to select an MLC block to transition to the SLC mode, or to select an MLC block to program. In another approach, a single count is maintained, where the SLC cycles are weighted less heavily than the MLC cycles.

Yield improvement through block budget optimization by using a transient pool of multi-level blocks

A storage system and method for improving read performance using multiple copies of a logical-to-physical address table are provided. In one embodiment, a method for parallelism is provided that is performed in a storage system comprising a plurality of memory areas accessible in parallel, wherein each memory area stores a copy of a logical-to-physical address table. The method comprises reading portions of the logical-to-physical address tables in parallel from the plurality of memory areas, wherein the portions comprise translations for logical addresses associated with a plurality of memory commands; translating the logical addresses associated with the plurality of memory commands into physical addresses using the read portions; and performing the plurality of memory commands. Other embodiments are provided.

Storage system and method for improving read performance using multiple copies of a logical-to-physical address table

A storage system and method for executing file-based firmware commands and collecting response data are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to: receive a request from a host in communication with the storage system to write data in a file, wherein the file is identified by a file path name; determine whether the file path name matches a predetermined file path name; in response to determining that the file path name does not match the predetermined file path name, write the data in the file; and in response to determining that the file path name matches the predetermined file path name, execute a command represented by the data. Other embodiments are provided.

Storage system and method for executing file-based firmware commands and collecting response data

A memory system may be configured to perform immediate folding of data from a low storage density area to a high storage density area. A low storage density target area may be monitored, and when a capacity of the low storage density target area reaches a threshold level, data stored in the low storage density target area may be folded to an associated high storage density target area. The memory system may utilize a pointer system to manage the folding of data. The pointer system may also be utilized for read operations in order to avoid updating address mapping tables for both the low storage density and the high storage density areas.

Folding operations in memory systems with single address updates

Technology is described herein for performing memory array operations in multiple memory dies in parallel. The memory dies, or groups of non-volatile memory cells on the memory dies, may exhibit different performance times for memory array operations. For example, non-volatile memory cells on one memory die may program more slowly than those on another memory die. The performance times of the memory dies (or groups of the memory cells on different memory dies) may be characterized relative to one another. Memory dies having similar performance times may be placed into the same meta-groups. Meta-groups may be formed at the die, zone, or block level. The meta-groups can be re-formed over the lifetime of the memory system, which can account for changes in performance times over the lifetime of the memory system.

Meta-groups in non-volatile storage based on performance times

A non-volatile memory system may include a controller configured for parsing a host file system, identifying a location of a host file system directory and tracking directory entries of files deleted from the host file system directory but having valid data mappings in the logical-to-physical mapping table. The controller may then store the location of the host file system directory, monitor activity in the host file system directory and track validity status information for use in optimizing a compaction process. The compaction process may include segregating into separate compaction destination blocks valid data based on the stored validity status such that data valid in both the host file system directory and the logical-to-physical mapping table is in compaction destination blocks separate from data having valid logical-to-physical mapping entries but associated with deleted host file system directory entries.

System and method for file detection and usage during compaction

In a multi-plane non-volatile memory, good blocks of different planes are linked for parallel operation for storing long host writes. Where bad blocks in one or more planes result in unlinked blocks, the unlinked blocks are configured for individual operation to store short host writes and/or memory system management data. Unlinked blocks may be configured as Single Level Cell (SLC) blocks while linked blocks may be configured as SLC blocks or Multi Level Cell (MLC) blocks.

Adaptive block allocation in nonvolatile memory

A non-volatile memory system may include a plurality of dies, where the plurality of dies are configured in a plurality of chip enable groups and at least one of the chip enable groups includes less than a maximum number of dies that may be uniquely identified according to a die selection scheme, where different memory arrays have different capacities and/or include memory elements of different types or technologies, or some combination thereof. One or more virtual die layouts, addressing schemes and mappings, wear leveling schemes, and initialization schemes may be employed for these multi-die configurations.

Addressing, interleave, wear leveling, and initialization schemes for different chip enables and memory arrays of different types

A non-volatile memory system may include a plurality of memory dies and a controller that is configured to write data into the memory dies according to a multi-die interleave scheme. A total number of the dies may be a non-multiple of a die component number of the interleave scheme. The controller may select abstract address based on a virtual die layout, and translate the abstract address to actual physical addresses. The translation may identify actual blocks located in different rows of blocks. The controller may also read data sets from the memory dies. To do so, the controller may translate an abstract address to actual physical addresses, which may similarly identify actual blocks located in different rows of blocks.

Physical addressing schemes for non-volatile memory systems employing multi-die interleave schemes

A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an error correction coding (ECC) decoder. The non-volatile memory is configured to sense hard bit data and soft bit data corresponding to multiple ECC codewords from a word line of the non-volatile memory and to sense soft bit data for the multiple ECC codewords. The soft bit data includes sub codes for each of the multiple ECC codewords. The non-volatile memory is configured to send less than all of the sensed soft bit sub codes to the ECC decoder.

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Bengaluru, India

Muralitharan Jayaraman