Seiko Epson Corporation

Muralikumar A Padaparambil

David Meltzer

Tat C Wu

Gregory A Blum

A method, algorithm, circuits, and/or systems for demodulation in an amplitude modulated (AM) radio receiver are disclosed. In one embodiment, a radio receiver can include an amplifier configured to receive a radio frequency (RF) input signal and a gain control signal, and provide an amplified signal, an automatic gain control (AGC) circuit configured to receive a high threshold comparator output and provide the gain control signal, a mixer configured to combine the amplified signal and a local oscillation signal and provide a mixed output, a high threshold comparator configured to compare the mixed output with a reference level and provide the high threshold comparator output, and a low threshold comparator configured to compare the mixed output with the reference level and provide an output of the radio receiver.

Dual threshold demodulation in an amplitude modulation radio receiver

A serializer includes a first stage configured to convert m-bit-wide parallel data into n-bit-wide parallel data, where n is 2, m&#x2267;2, x is an integer of at least 1, and y is an integer of at least 1, where the first stage includes a memory unit configured to store the m-bit-wide parallel in response to a timing signal and a first multiplexer configured to output the n-bit-wide parallel data in response to a frequency-multiplied derivative of the timing signal, and a current mode logic (CML) multiplexer stage configured to convert the n-bit-wide parallel data into serial data on successive transitions of n phase-shifted versions of the frequency-multiplied derivative of the timing signal.

Serializer architecture for serial communications

Apparatuses and methods for receiving an amplitude modulated signal in one of two modes depending on the quality of the received signal. In a first mode, the amplitude modulated signal is converted directly to a baseband signal. In a second mode, the amplitude modulated signal is converted to an intermediate frequency signal. The present invention advantageously combines direct conversion and image-rejection heterodyne receiver topologies with a relatively large degree of component reuse and relatively few additional components.

Dual demodulation mode AM radio

Circuits and methods convert parallel data into a serial data stream. A serializer according to the present invention generally includes a high speed section and a low speed section. The high speed section generally comprises a tree-based serializer configured to serialize an N-bit parallel data stream, where N is a power of two. The low speed section generally includes a data bank configured to load one or more samples of an M-bit parallel input stream, and a multiplexer configured to produce the N-bit parallel data stream from the data bank. The present invention advantageously provides high speed and relatively low power serialization of M-bit parallel data streams where M is not a power of two. In particular, the present invention advantageously provides high speed and relatively low power serialization of 10-bit parallel data streams.

Circuits and methods for high speed and low power data serialization

A CML master-slave latch incorporates logic into its master latching circuitry to incorporate a multiplexing function into the flip-flop. The multiplexing logic makes use of the pull-up loads and current source of the master latching circuitry. In this manner the pull-up loads and current source typically required for a stand-alone multiplexor are eliminated. Subsequently, the size of the present hybrid master-slave latch is smaller and consumes less power than a traditional combination of an independent multiplexor and master-slave latch. Since the master latching circuitry feeds only into the slave latching circuitry, the pull-up loads and the current sources of the master latching circuitry and slave latching circuitry may be optimized separately for achieving faster performance or less power consumption.

CMOS master/slave flip-flop with integrated multiplexor

A dual edge multiplexing flip-flop comprises a first circuit block having a first data input, a first clock signal input, a supply voltage input, and a ground connection; a second circuit block having a second data input, a second clock signal input, a supply voltage input, and a ground connection. Each circuit block is coupled to a common output node. When a common clock signal is input into the clock signal inputs, each circuit block outputs a floating voltage during one half of each clock cycle and a voltage indicative of a corresponding data input signal during the other half of each clock cycle.

Dual-edge triggered multiplexer flip-flop and method

A serializer for multiplexing 2data streams, each data stream having a frequency of f/(2), N being a positive integer. The serializer comprises 2&#x2212;1 instances of a dual-edge multiplexer flip-flop circuit, N frequency domains including a first frequency domain having the frequency f/2and a last frequency domain having a frequency f/2, and an output providing serialized data at frequency f clocked at half that rate. Thus, the highest clock signal frequency input into the serializer is f/2.

Low-power serializer with half-rate clocking and method

A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and is response to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration.

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Poughkeepsie, NY, United States of America

Muralikumar A Padaparambil