Intel Corporation

Azul Systems, Inc.

3dfx Interactive, Inc.

Nvidia Corporation

Murali Sundaresan

Feng Chen

Xiaoming Chen

Rajkishore Barik

Gil Tene

Michael A Wolf

Brian T Lewis

Jayanth N Rao

Mike B Macpherson

Jeffrey R Jackson

Cliff N Click, Jr

Altug Koker

Prasoonkumar Surti

Justin E Gottschlich

Thomas A Piazza

Mike MacPherson

Scott D Sellers

Leonard Truong

Jack H Choquette

Kevin B Normoyle

Supratim Pal

John M Danskin

Gary M Tarolli

James E Margeson, Iii

Manuel Olivier Gautho

Gary Tarolli

Elias Atmeh

A mechanism is described for facilitating efficient training of neural networks at computing devices. A method of embodiments, as described herein, includes detecting one or more inputs for training of a neural network, and introducing randomness in floating point (FP) numbers to prevent overtraining of the neural network, where introducing randomness includes replacing less-significant low-order bits of operand and result values with new low-order bits during the training of the neural network.

Training with adaptive runtime and precision profiling

A mechanism is described for facilitating smart distribution of resources for deep learning autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and introducing a library to a neural network application to determine an optimal point at which to apply frequency scaling without degrading performance of the neural network application at a computing device.

Tool for facilitating efficiency in machine learning

A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an I/O device page table.

Memory sharing via a unified memory architecture

A mechanism is described for facilitating smart collection of data and smart management of autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and combining a first computation directed to be performed locally at a local computing device with a second computation directed to be performed remotely at a remote computing device in communication with the local computing device over the one or more networks, where the first computation consumes low power, wherein the second computation consumes high power.

Smart autonomous machines utilizing cloud, error corrections, and predictions

A mechanism is described for facilitating smart distribution of resources for deep learning autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and introducing a library to a neural network application to determine optimal point at which to apply frequency scaling without degrading performance of the neural network application at a computing device.

Autonomous machines through cloud, error corrections, and predictions

In accordance with some embodiments, a scatter/gather memory approach may be enabled that is exposed or backed by system memory and uses conventional tags and addresses. Thus, such a technique may be more amenable to conventional software developers and their conventional techniques.

Scatter/gather capable system coherent cache

Determining a class of an object is disclosed. A pointer of the object is obtained. One or more bits that are not implemented as address bits are extracted from the pointer. The one or more bits are interpreted as an identifier of the class of the object. The class of the object is determined to correspond to the identifier.

Accelerated class check

Conversion of an array of structures (AOS) to a structure of arrays (SOA) improves the efficiency of transfer from the AOS to the SOA. A similar technique can be used to convert efficiently from an SOA to an AOS. The controller performing the conversion computes a partition size as the highest common factor between the structure size of structures in AOS and the number of banks in a first memory device, and transfers data based on the partition size, rather than on the structure size. The controller can read a partition size number of elements from multiple different structures to ensure that full data transfer bandwidth is used for each transfer.

Banked memory access efficiency by a graphics processor

Growing community of inventors

Sunnyvale, CA, United States of America

Murali Sundaresan