Intel Corporation

Murali S Talwai

Sundaravarathan R Iyengar

Mustafiz R Choudhury

Tsan-Kuen Wang

James F McKevitt, Iii

A processor capable of selecting between a write-back and a write-through mode of operation includes a bus interface unit for transferring information across the external bus. A local cache memory is coupled to the bus interface unit for storing information received from the bus interface unit. The processor also includes a control unit coupled to the cache memory and the bus interface unit. The control unit is operable to restart an interrupted operation from a point of interruption. A storage device coupled to the control unit stores a value corresponding to the point of interruption of the operation.

Growing community of inventors

Folsom, CA, United States of America

Murali S Talwai