Intel Corporation

Murali Ramadoss

Altug Koker

Joydeep Ray

Abhishek R Appu

Balaji Vembu

Prasoonkumar Surti

Michael Apodaca

Subramaniam M Maiyuran

Ankur N Shah

Karthik Vaidyanathan

Abhishek Venkatesh

Aditya Navale

Elmoustapha Ould-Ahmed-Vall

Ben J Ashbaugh

Eric C Samson

David M Puffer

Hema Chand Nalluri

Jeffery S Boles

Travis T Schluessler

Guei-Yuan Lueh

Jonathan Kennedy

Vikranth Vemulapalli

Jonathan D Pearce

Atsuo Kuwahara

Aravindh V Anantaraman

Hugues Labbe

Arthur Hunter, Jr

James A Valerio

Valentin Andrei

David J Cowperthwaite

Sungye Kim

William B Sadler

Vasanth Ranganathan

Nicolas C Galoppo Von Borries

Mike MacPherson

Brent E Insko

Bryan R White

Varghese George

Kun Tian

Peter L Doyle

Sameer Kp

Slawomir Grajewski

Joseph Koston

John H Feit

Eric J Hoekstra

Kamal Sinha

Zhi Hu Wang

Adam T Lake

Scott R Janus

Gabor Liktor

Ingo Wald

Devan Burke

Lakshminarayanan Striramassarma

Zack Waters

Deepak Shashidhar Vembar

Chandrasekaran Sakthivel

Andrew T Lauritzen

David M Cimini

Radhakrishnan Venkataraman

Anupreet S Kalra

Nikos Kaburlasos

Mahesh S Natu

Jacek Kwiatkowski

Pattabhiraman K

Niranjan L Cooray

Wei-Yu Chen

Saurabh Sharma

Daniel D Johnston

Jason M Surprise

Brandon L Fliflet

Kai Xiao

Arvind A Kumar

Zhi Jun Wang

James E Akiyama

John S Howard

Philip R Laws

Lakshminarayana Pappu

Tomasz Janczak

Brian T Lewis

Louis Feng

Todd M Witter

Kalyan Kumar Bhiravabhatla

Ping Liu

John J Valavi

Yoav Harel

Zhengmin Li

Ronald W Silvas

Rajesh M Sankaran

Prashant Sethi

Guy M Therien

Ajay V Bhatt

Rajeev K Nalawadi

Satish K Damaraju

Roman Surgutchik

Bryan E Veal

Gary Smith

Gary K Smith

Antonio S Cheng

Phani Kumar Kandula

Vidhya Krishnan

An infrastructure for a platform immersive experience is described. An example of an apparatus includes a microcontroller to receive control parameters for platform lighting options for a computing system and information regarding current system conditions for the computing system, and generate control instructions for a lighting pattern for a set of lights based at least in part on the control parameters and the information regarding current system conditions; and host control circuitry to receive the control instructions for the lighting pattern from the microcontroller, and provide control signals to control the set of lights.

Infrastructure for platform immersive experience

In one embodiment, a system on a chip integrated circuit (SoC) is provided that includes graphics processing resources including one or more graphics processing cores a memory subsystem including a memory controller, a physical interface, and a memory device and circuitry to dynamically adjust a voltage and frequency of the memory subsystem based on a workload executed by the graphics processing resources.

Dynamic voltage and frequency scaling for discrete graphics systems

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The graphics subsystem may include a first graphics engine to process a graphics workload, and a second graphics engine to offload at least a portion of the graphics workload from the first graphics engine. The second graphics engine may include a low precision compute engine. The system may further include a wearable display housing the second graphics engine. Other embodiments are disclosed and claimed.

Graphics system with additional context

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Controlling coarse pixel size from a stencil buffer

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

Systems and methods for improving cache efficiency and utilization

One embodiment provides a graphics processor comprising a system interface and circuitry coupled with the system interface. The circuitry includes an execution resource and a preemption status register. The execution resource is configured to execute an instruction. During execution of the instruction, the execution resource is to receive a request to preempt execution of a thread associated with the instruction and, based on a value stored in the preemption status register, execute at least one additional instruction after receipt of the request to preempt execution of the thread.

Page faulting and selective preemption

Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

Scalar core integration

One embodiment provides a parallel processor comprising a memory interface and a processing array coupled with the memory interface. The processing array is configured to address memory accessed via the memory interface via a virtual address mapping and includes circuitry to resolve a page fault for the virtual address mapping, wherein each of the multiple compute blocks is separately preemptable.

Examples described herein relate to a graphics processing system that includes one or more integrated graphics systems and one or more discrete graphics systems. In some examples, an operating system (OS) or other software supports switching between image display data being provided from either an integrated graphics system or a discrete graphics system by configuring a multiplexer at runtime to output image data to a display. In some examples, a multiplexer is not used and interface supported messages are used to transfer image data from an integrated graphics system to a discrete graphics system and the discrete graphics system generates and outputs image data to a display. In some examples, interface supported messages are used to transfer image data from a discrete graphics system to an integrated graphics system and the integrated graphics system uses an overlay process to generate a composite image for output to a display.

Switchable image source in a hybrid graphics systems

Methods and apparatus relating to techniques for repeating graphics render pattern detection are described. In an embodiment, a repeating pattern in a plurality of workload blocks is detected. Information corresponding to the plurality of workload blocks is stored and analyzed to determine a Dynamic Voltage Frequency Scaling (DVFS) sampling window of a processor. Other embodiments are also disclosed and claimed.

Repeating graphics render pattern detection

Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

Data prefetching for graphics data processing

Systems, apparatuses and methods may provide for technology that determines a frame rate of video content, sets a blend amount parameter based on the frame rate, and temporally anti-aliases the video content based on the blend amount parameter. Additionally, the technology may detect a coarse pixel (CP) shading condition with respect to one or more frames in the video content and select, in response to the CP shading condition, a per frame jitter pattern that jitters across pixels, wherein the video content is temporally anti-aliased based on the per frame jitter pattern. The CP shading condition may also cause the technology to apply a gradient to a plurality of color planes on a per color plane basis and discard pixel level samples associated with a CP if all mip data corresponding to the CP is transparent or shadowed out.

Synergistic temporal anti-aliasing and coarse pixel shading technology

Growing community of inventors

Folsom, CA, United States of America

Murali Ramadoss