Intel Corporation

Murali M Annavaram

Edward Thomas Grochowski

Hong Wang

Shih-Lien L Lu

John Thomas Shen

Chris Wilkerson

Gautham N Chinya

Richard A Hankins

Sanjiv M Shah

Ryan N Rakvic

David K Poulsen

Ed Grochowski

Gad Shlomo Sheaffer

Ronny Ronen

Doron Orenstein

Bryan P Black

Donald W McCauley

John P DeVale

A first execution time of a first thread executing on a first processing unit of a multiprocessor is determined. A second execution time of a second thread executing on a second processing unit of the multiprocessor is determined, the first and second threads executing in parallel. Power is set to the first and second processing units to effectuate the first and second threads to finish executing at approximately the same time in future executions of the first and second threads. Other embodiments are also described and claimed.

Load balancing for multi-threaded applications via asymmetric power throttling

Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

Method and apparatus for late timing transition detection

Embodiments of the invention are generally directed to systems, methods, and apparatuses for prefetching from a dynamic random access memory (DRAM) to a static random access memory (SRAM). In some embodiments, prefetch logic receives a prefetch hint associated with a load instruction. The prefetch logic may transfer two or more cache lines from an open page in the DRAM to the SRAM based, at least in part, on the prefetch hint.

Prefetching from dynamic random access memory to a static random access memory

Methods and systems to facilitate an efficient circuit for detecting internal timing errors for integrated devices, including a hierarchy of reporting the detection of the timing error from a circuit level to a functional unit block (FUB) level up to a global detection, and a reorder buffer (ROB) for storing a result for timing error recovery until the timing can be verified to be error free.

Method, system and apparatus for detecting and recovering from timing errors

A method and apparatus for changing the configuration of a multi-core processor is disclosed. In one embodiment, a throttle module (or throttle logic) may determine the amount of parallelism present in the currently-executing program, and change the execution of the threads of that program on the various cores. If the amount of parallelism is high, then the processor may be configured to run a larger amount of threads on cores configured to consume less power. If the amount of parallelism is low, then the processor may be configured to run a smaller amount of threads on cores configured for greater scalar performance.

Method and apparatus for varying energy per instruction according to the amount of available parallelism

Growing community of inventors

Santa Clara, CA, United States of America

Murali M Annavaram