Qualcomm Incorporated

Murali Krishna

Neven Klacar

Sujeev Dias

Dilip Venkateswaran Murali

Tony Truong

Thiyagarajan Selvam

Sandip HomChaudhuri

Arunn Coimbatore Krishnamurthy

Jean-Marie Quoc Danh Tran

Harinder Singh

Jitendra Prasad

Ravi Konda

Douglas Dahlby

BalaSubrahmanyam Chintamneedi

Yan He

A system includes an interface circuit configured to provide an interface with a link, and a controller. The controller is configured to receive one or more bandwidth requests from one or more clients, and determine at least one of a link speed and a link width for the link based on the one or more bandwidth requests.

Bandwidth based power management for peripheral component interconnect express devices

Systems and methods for power management for Peripheral Component Interconnect express (PCIE) devices allow PCIE termini to enter advanced low-power states while a PCIE link is idle. These advanced low-power states may include scaling a clock frequency up through a complete shutdown of power rails and clocks within the PCIE terminus. Additionally, use of a wakeup signal such as a clock request (CLKREQ or CLKREQ #) signal may allow the terminus to wake relatively quickly and resume operation so as to avoid degradation of the user experience or loss of data.

System power management for peripheral component interconnect express (PCIE)-based devices

Systems and methods for providing audio streams over peripheral component interconnect (PCI) express (PCIE) links are disclosed. In particular, exemplary aspects of the present disclosure are used to calculate an uplink timing requirement and adjust a margin time before a modem encodes audio data so that the encoding is done before data is transmitted to an external network. Further aspects of the present disclosure allow a first integrated circuit (IC) to synchronize its clock with that of the modem.

Audio streams over peripheral component interconnect (PCI) express (PCIE) links

The disclosure relates to minimizing power consumption of a WiFi system-on-chip (SOC) during idle periods. The disclosed architecture includes memory banks for the WiFi SoC's embedded processor that can be independently powered on/off and a Memory Management Unit (MMU) to translate virtual addresses to physical addresses and generate exceptions to process accesses to virtual addresses without a corresponding physical address. The architecture can implement a demand paging scheme whereby a MMU fault from an access to code/data not within the embedded memory causes the processor to fetch the code/data from an off-chip secondary memory. To minimize page faults, the architecture stores WiFi client code/data within the embedded processor's memory that is repeatedly accessed with a short periodicity or where there is an intolerance for delays of accessing the code/data.

WiFi memory power minimization

Link role determination in a dual-mode Peripheral Component Interconnect express (PCIe) device is disclosed. In this regard, determining a link role for a dual-mode PCIe device involves configuring the dual-mode PCIe device to operate in a root complex (RC) mode or an endpoint mode. The dual-mode PCIe device first performs a configuration and initiation sequence on a wire-based PCIe link in the RC mode. If the configuration and initiation sequence on the wire-based PCIe link is unsuccessful, then the dual-mode PCIe device invokes a random delay and switches to the endpoint mode at expiration of the random delay. By determining a link role of the dual-mode PCIe device based on the configuration and initiation sequence, it is possible to configure dynamically the dual-mode PCIe device to operate in the RC mode or the endpoint mode, thus allowing flexible configuration of the dual-mode PCIe device based on various application scenarios.

Link role determination in a dual-mode Peripheral Component Interconnect express (PCIe) device

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San Diego, CA, United States of America

Murali Krishna