Oracle America, Inc.

Murali Gala

Thomas Alan Ziaja

Paul J Dickinson

Karl P Dahlgren

Steven C Krow-Lucal

James C Hunt

Oliver Caty

David L Curwen

Poh-Joo Tan

An integrated circuit configured for at-speed scan testing of memory arrays. The integrated circuit includes a scan chain having a plurality of serially coupled scan elements, wherein a subset of the plurality of scan elements are coupled to provide signals to a memory array. Each scan element of the subset of the plurality of scan elements includes a flip flop having a data input, and a data output coupled to a corresponding input of the memory array, and selection circuitry configured to, in an operational mode, couple a data path to the data input, and further configured to, in a scan mode, couple to the data input one of a scan input, the data output, and a complement of the data output. The scan elements of the subset support at-speed testing of a memory array coupled thereto.

At-speed scan testing of memory arrays

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San Jose, CA, United States of America

Murali Gala