Cirrus Logic Inc.

Muraleedharan Ramakrishnan

Bhoodev Kumar

Vivek Oppula

Willem Zwart

Thomas H Hoff

Niju Alex Geevarughese

Synchronous, differential signaling may be performed over a communications path through a wired connection between a master device and a slave device to provide high-bandwidth and/or low-latency communications. Flexibility may be provided in the signaling protocol by providing for a configurable frame structure. Flexibility may be provided in mapping of data streams to bit slots in a frame, varying a number of downlink and uplink slots, configuring a number of turnarounds and locations of the turnarounds within a frame, configuring location and number of control word bit (CWB) slots in a frame, and/or adjusting a clock frequency of the communications link.

Synchronous differential signaling protocol

A synchronous clock edge alignment system and method increases detection coverage of transition delay faults that occur in logic circuits that have data released by a clock at an input of logic circuits internal to an integrated circuit and/or released at the output of the logic circuits when testing an integrated circuit. To increase detection coverage of inter-clock transition delay faults, in at least one embodiment, the synchronous clock edge alignment system and method align same transition type edges of internal data releasing clock signals, and at least two of the clock signals have different frequencies. By aligning the edges of the clock signals, transition delay faults that might otherwise not have occurred can be detected by, for example, a conventional circuit testing apparatus. Thus, aligning the edges of the clock signals increases detection of inter-clock transition delay faults.

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Austin, TX, United States of America

Muraleedharan Ramakrishnan