Intel Corporation

Muraleedhara Navada

Zale Theodore Schoenborn

Sanjay Dabral

Tim Frodsham

Timothy Frodsham

Sanjay Debral

Redundant acknowledgment between agents performing a loopback test over bidirectional communications bus is described. In one example, in a processor including a communications agent coupled to a bidirectional communications bus, the communications agent initiates loopback communications to a second agent, sends a packet including a redundant acknowledgment sequence to the second agent, receives the packet including the redundant acknowledgement sequence looped back from the second agent, determines whether the received redundant acknowledgment sequence is valid, sends a test sequence to the second agent, receives the test sequence looped back, and if the received redundant acknowledgment sequence is determined to be valid, then checks the received test sequence.

Redundant acknowledgment in loopback entry

Redundant acknowledgment between agents performing a loopback test over bidirectional communications bus is described. In one example the acknowledgment is performed by initiating loopback communications from a first agent to a second agent, sending a packet including a redundant acknowledgment sequence from the first agent to the second agent, receiving the packet including the redundant acknowledgement sequence looped back from the second agent at the first agent, sending a test sequence from the first agent to the second agent, and receiving the test sequence looped back from the first agent.

A condition is detected to cause a component having physical layer circuitry with a transmitter and a receiver to enter a testing state. The transmitter transmits a pre-selected data pattern while comparing data received by the receiver to the pre-selected data pattern during a first phase of the testing state. The transmitter transmits data received by the receiver without comparing the data received by the receiver to the pre-selected data pattern during a second phase of the testing state.

Compliance of master-slave modes for low-level debug of serial links

Methods and apparatuses for detecting an in-band reset using digital circuitry. A first counting circuit is coupled to receive a first clock signal and to generate output signals based on a number of cycles of the first clock signal. A second counting circuit is coupled to receive a second clock signal and the output signals from the first counting circuit. The second counting circuit generates output signals based on number of cycles of the second clock signal. A comparison circuit is coupled with to receive the output signals of the second counting circuit and to generate a reset signal if the output signals from the second counting circuit correspond to a pre-selected range.

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Bengaluru, India

Muraleedhara Navada