Intel Corporation

Muntaquim F Chowdhury

Douglas M Carmean

Robert J Greiner

Keshavan K Tiruvallur

Madhavan Parthasarathy

Brent E Lince

Dave L Hill

In a multi-threaded system, such as in a multi-processor system, different types of fences are provided to force completion of programmatically earlier instructions in a program. The types of fences can be thread-specific, and different types of fences are used based on different kinds of conditions, instructions, operations, or memory types. When a fence is executed, senior stores, request buffers, bus queues, or any combination of these stages in an execution pipeline can be drained. Fetches at a front end of the pipeline can also be killed to ensure that the bus queue can be drained.

Method and apparatus for multi-mode fencing in a microprocessor system

An apparatus in a first processor includes a first data structure to store addresses of store instruction dispatched during a last predetermined number of cycles. The apparatus further includes logic to determine whether a load address of a load instruction being executed matches one of the store addresses in the first data structure. The apparatus still further includes logic to replay to the respective load instruction if the load address of the respective load instruction matches of the store addresses in the first data structure.

Maintaining processor ordering by checking load addresses of unretired load instructions against snooping store addresses

According to one aspect of the invention, a method is provided in which store addresses of store instructions dispatched during a last predetermined number of cycles are maintained in a first data structure of a first processor. It is determined whether a load address of a first load instruction matches one of the store addresses in the first data structure. The first load instruction is replayed if the load address of the first load instruction matches one of the store addresses in the first data structure.

Method, apparatus, and system for maintaining processor ordering by checking load addresses of unretired load instructions against snooping store addresses

A system for write-combining uncacheable stores includes a memory order buffer, which receives first and second stores, and a data cache address and control, which receives the first and second stores from the memory order buffer. One of the memory order buffer and the data cache address and control determines whether the first and second stores are uncacheable and whether the first and second stores are contiguous in memory. If those conditions are satisfied, the data cache address and control write-combines the first and second stores before committing them to memory. The system may also apply additional conditions to determine whether the stores should be write-combined, for example requiring a minimum size for each store.

Growing community of inventors

Portland, OR, United States of America

Muntaquim F Chowdhury