Advanced Micro Devices Corporation

Munseork Choi

Hyeon-Seag Kim

Nian Niles Yang

Unsoon Kim

According to one exemplary embodiment, a two-bit memory cell situated over a substrate comprises a tunnel oxide layer situated over the substrate. The two-bit memory cell further comprises a first spacer and a second spacer situated over the tunnel oxide layer, where the first spacer is a first data bit storage location in the two-bit memory cell and the second spacer is a second data bit storage location in the two-bit memory cell. The first spacer and the second spacer may be, for example, silicon nitride or polycrystalline silicon. According to this exemplary embodiment, the two-bit memory cell further comprises an oxide layer situated between the first spacer and the second spacer. The two-bit memory cell further comprises a control gate situated over the oxide layer.

Structure and method for a two-bit memory cell

For fabricating a flash memory cell of an electrically programmable memory device on a semiconductor substrate, any region of a stack of a layer of tunnel dielectric material, a layer of floating gate material, a layer of floating dielectric material, and a layer of control gate material, not under a patterning structure, is etched away to form a tunnel dielectric structure comprised of the tunnel dielectric material disposed under the patterning structure, to form a floating gate structure comprised of the floating gate material over the tunnel dielectric structure, to form a floating dielectric structure comprised of the floating dielectric material disposed over the floating gate structure, and to form a control gate structure comprised of the control gate material disposed over the floating dielectric structure. The length of the floating gate structure is trimmed down from a first length of the patterning structure to a second length by etching away a portion of the floating gate material from at least one of a first sidewall and a second sidewall of the floating gate structure. A drain bit line junction of the flash memory cell is formed toward the first sidewall of the floating gate structure, and a source bit line junction of the flash memory cell is formed toward the second sidewall of the floating gate structure. The trim of the length of the floating gate structure minimizes the overlap of the floating gate structure over at least one of the drain bit line junction of the flash memory cell and the source bit line junction of the flash memory cell to minimize leakage of charge from the floating gate structure during programming or erasing of the flash memory cell.

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San Jose, CA, United States of America

Munseork Choi