Skhynix Inc.

Osong Medical Innovation Foundation, Korea University Research and Business Foundation

Munseon Jang

Dae Suk Kim

Jin Ho Jeong

Jongsun Park

Hoiju Chung

Chaehyeon Shin

A coding circuit includes an encoder circuit that generates parity by applying input data to a parity generating matrix and generate input codeword by concatenating the input data and the parity, and a decoder circuit that detects and corrects an out-of-boundary 2-bit error using syndromes. The out-of-boundary 2-bit error corresponds to two 1-bit errors occurred at two symbols respectively among a plurality of symbols included in output codeword, and the syndromes are generated by applying the output codeword to the parity generating matrix.

Coding circuit and memory device including the same

A memory includes a first check matrix calculation circuit configured to generate a first parity based on a group indicator portion of a check matrix and write data; a memory core including cell regions configured to store therein the write data and the first parity, neighboring ones of the cell regions sharing one or more sub-word line drivers; a first syndrome calculation circuit configured to generate a first syndrome based on the first parity read from the memory core and a first result of calculating the group indicator portion and data read from the memory core; and a failure determination circuit configured to detect, for each row of the memory core, a defective one of the sub-word line drivers based on the first syndrome.

Memory and operation method of memory

Disclosed is an operating method of a memory, and the operating method may include reading, from selected memory cells included in the memory, codewords including data and an error correction code; detecting errors in the codewords; correcting the errors in the codewords; re-writing the error-corrected codewords to the selected memory cells; re-reading the re-written error-corrected codewords from the selected memory cells; and determining whether the errors are permanent errors in response to a determination that an error is present in the re-read error-corrected codewords.

Memory including error correction circuit and operating method thereof

An error processing circuit includes: a first H matrix calculation circuit configured to calculate a first H matrix and upstream data to generate a partial first parity, during an encoding operation; a second H matrix calculation circuit configured to calculate a second H matrix and the upstream data to generate a second parity, during the encoding operation; and a parity calculation circuit configured to sum the partial first parity and the second parity to generate a first parity, during the encoding operation.

Error processing circuit, memory and operation method of the memory

A memory includes a first check matrix calculation circuit suitable for generating a first parity by calculating a group indicator portion of a check matrix and a write data; a memory core suitable for storing the write data and the first parity; a first syndrome calculation circuit suitable for generating a first syndrome by adding the first parity which is read from the memory core to a first calculation result obtained by calculating the group indicator portion and the data which is read from the memory core; and a failure determination circuit suitable for accumulating the first syndromes for a region of the memory core to generate a vector and determining a presence of a failure of the region based on the vector.

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Gyeonggi-do, South Korea

Munseon Jang