Skhynix Inc.

Munseon Jang

Hoiju Chung

Jang Ryul Kim

Hoi Ju Chung

A memory system includes a memory; and a memory controller which includes a spare buffer suitable for storing an error location in the memory and data at the location, and commands the memory to perform a spare read operation when a read operation needs to be performed in a region of the memory including the error location.

Memory, memory system and operation method of memory system

A method for operating a memory includes: reading data and an error correction code from a memory core; correcting an error of the read data based on the read error correction code to produce error-corrected data; generating new data by replacing a portion of the error-corrected data with write data, the portion becoming a write data portion; generating a new error correction code based on the new data; and writing the write data portion of the new data and the new error correction code into the memory core.

Memory and operation method of memory

A memory includes: a memory core; an error correction circuit suitable for correcting, when a number of one or more errors detected in data read from the memory core is equal to or greater than a threshold value, the detected errors based on an error correction code read from the memory core to produce an error-corrected data; and a data transferring circuit suitable for: outputting, when the detected errors are corrected, the error-corrected data according to a long read latency, and outputting, when the number of the detected errors is less than the threshold value or no error is detected in the read data, the read data according to a short read latency.

Memory system, integrated circuit system, and operation method of memory system

A memory includes: a non-volatile memory suitable for storing a defect address; a register suitable for receiving and storing the defect address from the non-volatile memory during a boot-up operation, and receiving and storing an address that is input from an exterior during a register access operation; a comparison circuit suitable for comparing the address stored in the register with an address that is input from the exterior to produce a comparison result; redundant memory cells that are accessed according to the comparison result of the comparison circuit and a redundancy activation bit; and normal memory cells that are accessed according to the comparison result of the comparison circuit and the redundancy activation bit.

Memory, memory system, and operation method of memory system

A memory which includes a downlink error correction circuit suitable for correcting an error in data transferred from a memory controller based on a downlink error correction code transferred from the memory controller to produce an error-corrected data so that when an uncorrectable error is detected in the downlink error correction circuit of the memory or when an uncorrectable error is detected in the memory error correction circuit of the memory, the information that there is an uncorrectable error may be transferred to the memory controller in the memory system by using an uncorrectable error signal and an error flag signal, thus, improving the reliability of the memory system.

Memory, memory system, and operation method of memory

A method for operating a memory includes: activating a first row, and sensing and amplifying, by a first bit line sense amplifier array, data of memory cells of the first row; transferring data of first columns of the first row from the first bit line sense amplifier array to global input/output lines through first input/output sense amplifiers; storing data of the global input/output lines in the first columns of a dummy bit line sense amplifier array through dummy write drivers; transferring data of second columns of the first row from the first bit line sense amplifier array to the global input/output lines through the first input/output sense amplifiers; and storing the data of the global input/output lines in the second columns of the dummy bit line sense amplifier array through the dummy write drivers.

A memory includes: a memory core including sequentially disposed N data cell regions and an ECC cell region respectively suitable for storing N data pieces of K bits and a corresponding ECC of M bits; and an error correction circuitry suitable for generating the ECC based on the data pieces and error-correcting the data pieces based on the ECC, through a check matrix configured by a message part of a [M&#xd7;(K*N)] bit-dimension and an ECC part of a [M&#xd7;M] bit-dimension, wherein the message part includes N characteristic indicator groups of a [M/2&#xd7;K] bit-dimension, respectively corresponding to the data pieces, and each including K indicators of a [M/2&#xd7;1] bit-dimension and having the same value, and wherein a hamming distance between the indicators respectively corresponding to the data pieces stored in neighboring ones among the data cell regions is 1 or M/2.

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San Jose, CA, United States of America

Munseon Jang