International Business Machines Corporation

Infineon Technologies Ag

Munir-ud-Din Naeem

Dureseti Chidambarrao

Johnathan E Faltermeier

David M Dobuzinsky

Chienfan Yu

Rajesh Rengarajan

Matthew J Sendelbach

Michael Maldei

Prakash Chimanlal Dev

Thomas Rupp

John Preston Benedict

Ting-Hao Wang

An etch rate of a nitride liner layer is improved relative to an etch rate of a nitride cap layer. The nitride liner layer is located at an exposed portion of a substrate adjacent to a stacked structure also located atop the substrate. The nitride cap layer is located atop the stacked structure. An oxide spacer is formed along sidewalls of the stacked structure. The nitride liner layer is patterned and etched to form at least one opening therein to the substrate while the nitride cap layer remains substantially intact.

Method of reducing erosion of a nitride gate cap layer during reactive ion etch of nitride liner layer for bit line contact of DRAM device

A reactor for corona destruction of volatile organic compounds (VOCs), a multi-surface catalyst for the reactor and a method of making the catalyst for the reactor. The reactor has a catalyst of a high dielectric material with an enhanced surface area. A catalyst layer stack is formed by depositing a high dielectric layer on a substrate and, then depositing a conductive layer on the dielectric layer. The catalyst layer stack is bombarded by low RF energy ions to form an enhanced surface area and to form a protective layer over the conductive layer. Catalyst layer stacks may be joined back to form double-sided catalyst layer stacks. The catalyst layer stack may be diced into small pieces that are used in the reactor or the whole catalyst layer stack may be used.

Catalytic reactor

Method of making dielectric catalyst structures

The occurrence of defects in interconnect metal structure is reduced or eliminated by a method wherein a semiconductor substrate having a dielectric layer, a metal-containing electrically conductive layer and a patterned photoresist layer, the metal-containing electrically conductive layer overlying the dielectric layer and the photoresist layer overlying the conductive layer such that portions of the conductive layer are exposed, is treated using a sequence of at least four reactive ion etching environments, each having a different etchant composition from the previous and/or subsequent environment. The invention is especially applicable for metal interconnect structures having aluminum and/or copper as the primary conductive layer.

Method of reducing metal voids in semiconductor device interconnection

A process for making metal lines in BEOL semiconductor devices. The process reduces metal voids in the metal lines. In one embodiment, metal lines, including a top barrier blanket are formed over an interlevel dielectric. An insulating layer having tensile stress is formed over the metal lines. A first compressive oxide layer is formed over the insulating layer, wherein the insulating layer provides a tensile stress on the metal lines and the compressive oxide layer provides a compressive stress on the metal lines resulting in reduction of metal voids. The compressive oxide layer is etched with a first type of gas until the insulating layer is reached. The insulating layer is etched with addition of gases to facilitate end-point detection. This second type of gas is monitored for an emission of species at an intensity level having a specific wavelength optical emission, and the etching is stopped when the intensity level is reached.

Reducing metal voids during BEOL metallization

Dielectric catalyst structures

A collar oxide is formed in a provided a semiconductor substrate having (3) a partially full trench, (2) (i) fill surface defined by fill material partially filling said trench, (ii) upper surface outside of said trench, and (iii) trench sidewall surface not covered by said fill material, and (3) a conformal oxide layer overlying said fill, upper, and sidewall surfaces, by selectively etching as follows:

High selectivity collar oxide etch processes

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Poughkeepsie, NY, United States of America

Munir-ud-Din Naeem