Nec Corporation

Elpida Memory, Inc.

Renesas Electronics Corporation

Keio University

Muneo Fukaishi

Hiroaki Ikeda

Masayuki Mizuno

Kayoko Shibata

Yasuhiko Hagihara

Hideaki Saito

Hideki Sasaki

Yoshihiro Nakagawa

Tadahiro Kuroda

Masato Motomura

Eiji Hankui

Toshihide Kuriyama

Toru Taura

Hikaru Hida

Kouichi Yamaguchi

Masakazu Yamashina

Yoshiharu Aimoto

Kazuhisa Sunaga

Provided on a chip are a plurality of conductor patterns for forming a coil, and a connection-relationship control device for controlling connection between adjacent conductor patterns. By switching the connection relationship of the conductor patterns by the connection-relationship control device, it is possible to form a coil of a desired shape at a desired position.

Integrated circuit device

Disclosed is a semiconductor integrated circuit device including a transmitting circuit and a receiving coil inductively coupled to a transmitting coil. The transmitting circuit transmits data by supplying a current through the transmitting coil not at the time of transition of data but at every rising edge or falling edge of a clock used in transmission of data. At every rising edge or falling edge of the clock, a receiving circuit captures a voltage induced in the receiving coil due to the current flowing through the transmitting coil, reproduces the transmitted data and outputs the reproduced data.

Signal transmission system and semiconductor integrated circuit device

An interface circuit, which uses electromagnetic induction to perform a signal transmission, comprises a transmission coil and a transmission circuit that provides a signal to the transmission coil, thereby causing the transmission coil to output a triangular or roughly triangular magnetic field signal.

Transmission method, interface circuit, semiconductor device, semiconductor package, semiconductor module and memory module

A common mode of a waveform of a duobinary transmission signal (IN) is set to 0 and the size of a data eye is set to Veye; and reference potentials Vref_H and Vref_L are set to the following values:eye/&#x221a;{square root over (3)}&#x2266;refeye/&#x221a;{square root over (2)}&#x2003;&#x2003;(1)&#x2212;eye/&#x221a;{square root over (2)}&#x2266;refeye/&#x221a;{square root over (3)}&#x2003;&#x2003;(2) More particularly, effect becomes remarkable by setting the reference potentials Vref_H and Vref_L to central values in ranges shown in Equations (1) and (2), respectively. In the central values, fluctuation (jitter) of transition data becomes the smallest, and a jitter characteristic of a reproducing clock becomes the best. Consequently, a clock reproducing apparatus in which a received clock from duobinary transmission data is reproduced with high accuracy is provide.

Clock reproducing apparatus and method

There are provided a semiconductor device and a semiconductor chip, in which the interconnection is made to be highly reliable by stacking three or more layers of chips without contact therebetween. A semiconductor chip of the present invention comprises a first signal transmission circuit, a silicon substrate on which a first changeover switch is formed, and an interconnection layer on which a first capacitive-coupling upper electrode is formed, wherein a first capacitive-coupling lower electrode is additionally formed on the rear surface of the silicon substrate through a first via hole that penetrates the silicon substrate and, whereas the first capacitive-coupling upper electrode is directly connected to the first signal transmission circuit, the first capacitive-coupling lower electrode is connected to the first signal transmission circuit through the first via hole and through the first changeover switch.

Semiconductor chip and semiconductor device

A memory system has a memory controller and a plurality of memories. The plurality of memories are connected via a switch to an end of a bus, which is connected to the memory controller, wherein the plurality of memories are controlled by the switch. By suppressing reflection and loads on the bus, a higher data transmission speed can be obtained.

High-speed memory system

A stacked semiconductor device includes a plurality of semiconductor chips and a conductive path extending through at least one of the semiconductor chips. The semiconductor chips are stacked together. The semiconductor chips are electrically connected by the conductive path, and the conductive path has a plurality of through-connections extending through the corresponding semiconductor chip.

Stacked semiconductor device

In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal transmission between these semiconductor circuit chips, when transmitting signals, only one interchip interconnection that serves for signal transmission is selected and other interchip interconnections are electrically isolated by means of switches that are provided between the interchip interconnections and signal lines. Interchip interconnection capacitance relating to the charge and discharge of interconnections is thus minimized.

Three-dimensional semiconductor device provided with interchip interconnection selection means for electrically isolating interconnections other than selected interchip interconnections

The stacked semiconductor memory device of the present invention has the object of reducing the cost of developing a wide variety of memory devices and includes: a memory cell array chip that is equipped with memory cell arrays, an interface chip that is stacked with the memory cell array chip and that is provided with a memory configuration switching circuit for changing the input/output bit configuration of the memory cell arrays, and a plurality of interchip wires for connecting the memory cell array chip and the interface chip.

Stacked semiconductor memory device

A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.

In a phase locked loop circuit, a phase difference signal (an up signal and a down signal) is supplied from a phase comparator to a serial-to-parallel converting circuit, and an output of the serial-to-parallel converting circuit is supplied to an up-down counter having a count value is counted up or down in accordance with the phase difference detected by the phase comparator. A voltage controlled oscillator generates an oscillation signal having the frequency controlled in accordance with the count value of the up-down counter. Thus, since the phase difference signal is serial-to-parallel converted, the rate of the phase difference signal is lowered, so that the operation speed of the up-down counter can be relaxed. Therefore, the operation speed of the phase locked loop circuit can be elevated with elevating the operation speed of the up-down counter.

Phase locked loop circuit

In a phase comparator, a first data fetching circuit fetches an input signal in response to a transition timing of a clock signal having a frequency about half that of the input signal, and a second data fetching circuit fetches the output signal of the first data fetching circuit in response to a transition timing of an inverted signal of the clock signal. A first exclusive OR performs an exclusive OR operation upon the input signal and the output signal of the first data fetching circuit. and a second exclusive OR circuit performs an exclusive OR operation upon the output signals of the first and second data fetching circuits. An inverter inverts the output signal of the first exclusive OR circuit. A first AND circuit performs an AND operation upon the output signal of the second data fetching circuit and the output of the exclusive OR circuit, a second AND circuit performs an AND operation upon the output signal of the first exclusive OR circuit and the output of the first AND circuit to generate a leading signal, and a third AND circuit performs an AND operation upon the output signal of the inverter and the output of the,first AND circuit to generate a lagging signal.

Phase comparator operable at half frequency of input signal

In a voltage controlled oscillator including an odd number of inverter circuits connected in a ring shape, at least one of the inverter circuits is constructed by an inverter and a current control circuit connected in series between a pre-stage inverter circuit and post-stage inverter circuit, and a voltage control circuit connected between the pre-stage inverter circuit and the post-stage inverter circuit. The inverter receives an output signal of the pre-stage inverter circuit to generate an inverted signal. The current control circuit supplies a current in accordance with the inverted signal to the post-stage inverter circuit. The current is controlled by an input voltage. The voltage control circuit charges and discharges an input capacitance of the post-stage inverter circuit in accordance with the output signal of the pre-stage inverter circuit.

Voltage controlled oscillator including ring-shaped inverter circuits

A metal-semiconductor type field effect transistor has a Y-letter shaped gate electrode standing on an active layer, and the Y-letter shaped gate electrode prevents piezoelectric charges induced beneath both ends of the wing portions thereof from undesirable merger so as to restrict variation of the threshold regardless of the orientation of the Y-letter shaped gate electrode.

Compound semiconductor field effect transistor free from piezoelectric

The main surface of a semiconductor substrate, on which a field effect transistor is formed, coincides with the (nm0) lattice plane of the substrate and drain electrode thereof is oriented to flow drain current in a direction parallel to the [mn0] or [mn0] axis, wherein n and m independently represent an arbitrary integer, provided that n and m are not 0 at the same time, and that the quotient n/m (m is not zero) is not an integer. Accordingly, the plane orientation of the substrate and the direction of the drain current have a relationship such that no piezoelectric charges are induced in the channel region of the field effect transistor. Therefore, substantially no piezoelectric charges are generated even when a stress is produced in the dielectric layer formed on the substrate. Moreover, deterioration and variation in the electric characteristics due to the variation in the thickness of the dielectric layer are minimized.

Growing community of inventors

Tokyo, Japan

Muneo Fukaishi