Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Munenori Sakai

Shigeo Imai

Shinji Fujii

Naoya Waki

Akio Sakata

According to one embodiment, a semiconductor circuit includes a first transimpedance amplifier and a second transimpedance amplifier. The first transimpedance amplifier is configured to convert an input current to a first output voltage and output the first output voltage from a first output terminal when a reference voltage is supplied to a first input terminal and the input current is supplied to a second input terminal. The second transimpedance amplifier has a circuit configuration similar to a circuit configuration of the first transimpedance amplifier. The second transimpedance amplifier is configured to output a second output voltage from a second output terminal when the reference voltage is supplied to a third input terminal.

Semiconductor circuit

In a device, a first transistor has a gate connected to an input. A first resistance is connected between one end of the first transistor and a first power supply line. A second resistance is connected between the other end of the first transistor and the second power supply line. A second transistor has a gate connected to a first node between the first transistor and the first resistance, and one end thereof is connected to the first power supply line. A current source is connected to the other end of the second transistor and the second power supply line. An inverter circuit has an input part connected to a second node between the second transistor and the current source, has an output part connected to an output, and outputs a voltage on any of the first power supply line or the second power supply line from the output.

Integrated circuit device

A protective circuit includes a first line, a second line, and a signal line. A first and second diode are connected in series between the first and second lines. A resistor and a capacitor are connected between the first and second lines. A first inverter, a second inverter, a third inverter are connected in series between a node between the resistor and capacitor and a gate of a first transistor. A third diode is connected between the first and second lines. The first transistor is connected between the first and second lines. A second transistor is connected between the first line and a protected circuit. A gate of the second transistor is connected to the output of the first inverter. A third transistor is connected between the second line and the protected circuit. A gate of the third transistor is connected to output of the second inverter.

Protective circuit

A semiconductor device of an embodiment includes: a plurality of power lines extending in a first direction; and a plurality of cells arrayed along the first direction and a second direction intersecting the first direction and having a cell height of an integer multiple of a distance between the power lines adjacent to each other in the second direction, the cell height being a dimension in the second direction, wherein the plurality of cells include: a functional cell that contributes to a function of the semiconductor device; and a capacitance cell including a diffusion region of a first conductivity type and a gate electrode stacked above the diffusion region, and functioning as a decoupling capacitor, the capacitance cell is configured as a multi-height cell having a cell height of two or more times the distance, the capacitance cell includes a plurality of overlapping regions that are regions of the gate electrode overlapping the diffusion region in a stacking direction, the overlapping regions being aligned in the second direction, and the plurality of overlapping regions are arranged in one continuous well of a second conductivity type different from the first conductivity type.

Growing community of inventors

Kanagawa, Japan

Munenori Sakai