Kabushiki Kaisha Toshiba

International Business Machines Corporation

Sony Computer Entertainment Inc.

Toshiba American Electronic Components, Inc.

Munehiro Yoshida

Yohji Watanabe

Daisuke Kato

David William Boerstler

Charles Ray Johns

Michael Fan Wang

Kazuaki Yazawa

Hiroki Kihara

Iwao Takiguchi

Tetsuji Tamura

Takashi Taira

Hiroshi Shinya

Kenji Ishizuka

Toshiaki Kirihata

Daniel Lawrence Stasiak

Mitsuhiro Koga

Mariko Kaku

Daisuke Katoh

Melia F Gordon

Methods, systems and thermal sensing apparatus are provided that use bandgap voltage reference generators that do not use trimming circuitry. Further, circuits, systems, and methods in accordance with the present invention are provided that do not use large amounts of chip real estate and do not require a separate thermal sensing element.

Thermal sensing circuit using bandgap voltage reference generators without trimming circuitry

Systems and methods for positioning thermal sensors within an integrated circuit in a manner that provides useful thermal measurements corresponding to different parts of the integrated circuit. In one embodiment, an integrated circuit includes multiple, duplicate functional blocks. A separate thermal sensor is coupled to each of the duplicate functional blocks, preferably in the same relative location on each of the duplicate functional blocks, and preferably at a hotspot. One embodiment also includes thermal sensors on one or more functional blocks of other types in the integrated circuit. One embodiment includes a thermal sensor positioned at a cool spot, such as at the edge of the integrated circuit chip. Each of the thermal sensors may have ports to enable power and ground connections or data connections between the sensors and external components or devices.

Systems and methods for thermal sensing

Thermal sensing circuits using bandgap voltage reference generators without trimming circuitry

Systems and methods for reducing the complexity and size of thermal sensors, where the voltage of a thermally sensitive device is compared to a reference voltage that varies as a function of temperature, rather than being constant. One embodiment comprises a thermal sensing system including a reference voltage generator, a thermal sensor and a comparator. The reference voltage generator is configured to generate a non-constant reference voltage that varies as a known function of temperature. The thermal sensor is configured to generate a sensor voltage that also varies as a known function of temperature. The functions of the reference and sensor voltages cross at a known temperature/voltage. The comparator is configured to compare the sensor voltage and the reference voltage and to generate a comparison output signal based on the comparison of the sensor voltage and the first reference voltage. A transition in this signal indicates the reference temperature.

Advanced thermal sensor

The present invention provides an integrated circuit. The integrated circuit has a plurality of chip areas. The integrated circuit also has a plurality of temperature sensors, at least one per chip area. The temperature sensors generate a voltage proportional to the measured temperature. A voltage comparator compares the voltage output of the plurality of temperature sensors. The voltage comparator is further employable to generate a signal if the difference between the voltages generated by the plurality of temperature sensors exceeds a threshold.

Thermal sensing method and system

An integrated circuit die is disclosed including a temperature detection circuit and a memory configured to store calibration data. The temperature detection circuit is operatively coupled to the memory, and receives an input signal. The temperature detection circuit is configured to produce an output signal dependent upon the input signal and indicative of whether a temperature of the integrated circuit die is greater than a selected temperature. During a normal operating mode of the integrated circuit die the input signal comprises the calibration data. A system and methods for calibrating the temperature detection circuit are also described.

Integrated circuit die including a temperature detection circuit, and system and methods for calibrating the temperature detection circuit

A semiconductor storage device has a function of simultaneously activating a plurality of word lines connected to the same bit line via cell transistors. The semiconductor storage device comprises a column redundancy system that sets repair regions of column redundancy based on row addresses. By the column redundancy system, the repair regions are set to cause the plurality of word lines which can be activated together to belong to the same repair region, when the repair regions are set to divide the bit line.

Semiconductor storage device formed to optimize test technique and redundancy technology

A semiconductor memory device is disclosed which comprises a cell array including a normal data section used for normal data write and read and a parity data section used for check data write and read, the check data being for execution of error check of data as read out of the normal data section, a data buffer for temporal stage of read data from the cell array and write data into the cell array, and an ECC circuit for generating the check data to be stored in the parity data section from write data as input during data writing, and for performing error check and correction of data read out of the normal section based on the data read out of the normal data section and the check data read out of said parity data section during data reading. N-bit parallel data transfer is performed between the data buffer and normal data section whereas m-bit parallel data transfer is done between the data buffer and external input/output terminals (where m and n are integers satisfying m&#x3c;n).

Semiconductor memory device

There is provided a semiconductor storage device in which only a defective element is replaced by a row redundant element to compensate for a defect if at least one of a plurality of elements is defective in a case where the plurality of elements in a memory cell array are simultaneously activated. The semiconductor storage device includes an array control circuit which is configured to interrupt the operation of the defective element by preventing a word line state signal from being received based on a signal to determine whether a row redundancy replacement process is performed or not. The word line state signal is input to the plurality of memory blocks in the cell array unit via a single signal line.

A semiconductor memory device has a cell array, first normal elements each defined within the cell array as a group of memory cells arranged in a first direction of the cell array, second normal elements each defined within the cell array as a group of memory cells arranged in a second direction of the cell array, each the second normal element selecting a memory cells in operative association with a corresponding one of the first normal elements, first redundant elements disposed for replacement of defective first normal elements within the cell array, and second redundant elements disposed for replacement of defective second normal elements within the cell array. There are defined within the cell array first/second repair regions as a group of first/second normal elements with permission of replacement by each first/second redundant element.

A semiconductor memory device has a cell array, first normal elements each defined within the cell array as a group of memory cells arranged in a first direction of the cell array, second normal elements each defined within the cell array as a group of memory cells arranged in a second direction of the cell array, each the second normal element selecting a memory cells in operative association with a corresponding one of the first normal elements, first redundant elements disposed for replacement of defective first normal elements within the cell array, and second redundant elements disposed for replacement of defective second normal elements within the cell array. There are defined within the cell array first/second repair region as group of first/second normal elements with permission of replacement by each first/second redundant element.

Semiconductor memory device having redundancy system

An internal row address signal is generated by a refresh address counter and supplied to a row decoder. In a normal refresh operation, the refresh address counter sequentially increments the internal row address signal on the basis of a trigger signal. As a result, the data in all memory cells is refreshed. In a low-consumption-current refresh operation, at least one of the bits of the internal row address signal is fixed. Hence, the refresh operation is executed only for the memory cells of a predetermined refresh area.

Semiconductor memory having refresh function

To provide a semiconductor memory for synchronizing input of a command except for POWER-DOWN-EXIT or the like and write or read of data with an external clock and generating a column operation synchronous pulse having the same number as that of a burst length within the semiconductor memory by using an internal operation synchronous pulse having this external clock as a trigger and after activation of a column system circuit, using the internal operation synchronous pulse as a trigger. This semiconductor memory uses column pulse transfer signals, which are different between read and write to control a column system circuit.

Synchronous DRAM using column operation sychronous pulses which are different between read and write

A memory chip is comprises memory cells and, for example, 16 amplifiers, each having a first output terminal and a second output terminal. The 16 amplifiers are connected at the first output terminal to 16 first-type signal lines RD(,) to RD(,) and at the second output terminal to four second-type signal lines bTRD(,) to bTRD(,) in increment fashion. More precisely, the second output terminals of every four amplifiers are connected the four second-type signal lines, respectively. A coincidence/non-coincidence determining circuit determines how the potentials of the second-type signal lines bTRD(,) to bTRD(,) and the potentials of the first-type signal lines RD(,) to RD(,) connected to all amplifiers that are connected to the second-type signal lines change when all data items of the same polarity are read from memory cells. Hence, a compressed-data test can be performed thereby compressing 16-bit data into 4-bit data by using only 20 signal lines.

An improved data sense for a DRAM. Each bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level.

Growing community of inventors

Austin, TX, United States of America

Munehiro Yoshida