Semiconductor Energy Laboratory Co., Ltd.

Munehiro Kozuma

Yoshiyuki Kurokawa

Takayuki Ikeda

Takeshi Aoki

Hikaru Tamura

Takanori Matsuzaki

Masataka Ikeda

Shunpei Yamazaki

Takashi Nakagawa

Yuki Okamoto

Kei Takahashi

Ryota Tajima

Tatsuya Onuki

Daisuke Kawae

Hiroki Inoue

Masami Endo

Takayuki Inoue

Hiroki Dembo

Fumika Akasawa

Takuro Kanemura

Seiichi Yoneda

Takahiko Ishizu

Masashi Fujita

Mayumi Mikami

Shuji Fukai

Shintaro Harada

Minato Ito

Sho Nagao

Shuhei Nagatsuka

Susumu Kawashima

Hidetomo Kobayashi

Atsushi Miyaguchi

Yutaka Okazaki

Takashi Hamada

Takahiro Fukutome

Yohei Momma

Masashi Oota

Hitoshi Kunitake

Tatsunori Inoue

Kazuma Furutani

Akio Suzuki

Seiya Saito

Kousuke Sasaki

Yusuke Koumura

Kazuko Yamawaki

An electronic device with a novel structure is provided. The electronic device includes a display apparatus, a gaze detection portion, and an arithmetic portion. The display apparatus includes a display portion divided into a plurality of sub-display portions and a functional circuit including a luminance conversion circuit. The gaze detection portion has a function of detecting the user's gaze. The arithmetic portion has a function of allocating the plurality of sub-display portions to a first section or a second section with the use of the detection result of the gaze detection portion. The functional circuit has a function of performing display on the sub-display portion included in the first section with a first driving frequency and performing display on the sub-display portion included in the second section with a second driving frequency lower than the first driving frequency. The luminance conversion circuit has a function of converting image data displayed on the second section to image data with reduced luminance to be displayed in the sub-display portion.

Electronic device

A battery control circuit with a novel structure, a battery protection circuit with a novel structure, and a power storage device including either of the battery circuits are provided. The power storage device includes a first circuit portion, a second circuit portion, a third circuit portion, and a secondary battery; the first circuit portion has a function of controlling charging of the secondary battery; the first circuit portion has a function of supplying the start time and the end time of the charging of the secondary battery to the third circuit portion; the second circuit portion has functions of generating a first voltage and a first current and supplying them to the third circuit portion; the third circuit portion has a function of generating a second voltage by charging the first current in a capacitor; and the third circuit portion has a function of comparing the first voltage and the second voltage.

Power storage device and method for operating power storage device

A novel semiconductor device that is highly convenient or reliable is provided. The semiconductor device includes a sensor unit, a first memory unit, a second memory unit, and a determination unit. The sensor unit supplies a sensor signal, the first memory unit retains the sensor signal, the second memory unit retains standard data and allowable difference information, the determination unit compares the sensor signal with the standard data, and the determination unit supplies a control signal in the case where a difference between the sensor signal and the standard data exceeds the allowable difference information.

Semiconductor device sensor unit

A display apparatus with a novel structure is provided. The display apparatus includes a first layer and a second layer positioned above the first layer. The first layer includes a driver circuit region, and the second layer includes a pixel array. The pixel array includes a plurality of pixel regions. The driver circuit region includes a control circuit unit and a plurality of local driver circuits. One of the plurality of local driver circuits corresponds to any one of the plurality of pixel regions. The local driver circuit has a function of outputting a driving signal for driving a plurality of pixels included in the corresponding pixel region. The control circuit unit has a function of comparing definition data of an input image signal and aspect ratio data of the pixel array to determine a first region where display is performed and a second region where display is not performed, and outputting, to the local driver circuit corresponding to the second region, a control signal for stopping output of the driving signal.

Display apparatus and electronic device

To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.

Semiconductor device

A high-resolution display device in which delay of input signals to pixels is reduced is provided. In the display device, a first layer, a second layer, and a third layer are formed in this order from the bottom. The first layer includes a driver circuit and a plurality of first wirings, the second layer includes a plurality of first contact portions, and the third layer includes a pixel array and a plurality of second wirings. The pixel array includes a plurality of pixel circuits. The plurality of second wirings are parallel to each other and extended in the column direction of the pixel array, and the plurality of pixel circuits are electrically connected to the plurality of second wirings. The driver circuit includes a plurality of output terminals positioned along a first direction. The plurality of first wirings are extended perpendicular to the first direction, and the plurality of output terminals are electrically connected to the plurality of first wirings. The plurality of first wirings are electrically connected to the plurality of second wirings through the plurality of first contact portions.

Display device and electronic device

A semiconductor device having redundancy is provided. The semiconductor device includes a first driver circuit, a second driver circuit, a first selection circuit, a second selection circuit, and a switch circuit. An output terminal of the first driver circuit is electrically connected to an input terminal of the first selection circuit and a first terminal of the switch circuit, and an output terminal of the second driver circuit is electrically connected to an input terminal of the second selection circuit and a second terminal of the switch circuit.

Semiconductor device, display apparatus, and electronic device

A semiconductor device capable of performing product-sum operation with high layout flexibility is provided. In the semiconductor device, a first layer, a second layer, and a third layer are formed in this order. The first layer includes a first cell, a first circuit, a first wiring, and a second wiring adjacent to the first wiring. The second layer includes a third wiring and a fourth wiring adjacent to the third wiring. The third layer includes an electrode and a sensor. The first circuit includes a switch. The sensor is electrically connected to the third wiring through the electrode and a first plug, a first terminal of the switch is electrically connected to the third wiring through a second plug, and a second terminal of the switch is electrically connected to the first cell through the first wiring. The electrode includes a region overlapping with the sensor and a region overlapping with the first plug. Note that the first to fourth wirings are parallel to each other, and the distance between the third wiring and the fourth wiring is greater than or equal to 0.9 times and less than or equal to 1.1 times the distance between the first wiring and the second wiring.

Semiconductor device and electronic device

In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.

Semiconductor device and manufacturing method thereof

A semiconductor device with reduced power consumption is provided. With three transistors, potentials of two nodes are switched and a voltage is detected. One of a source and a drain of a first transistor is electrically connected to a first terminal. The other of the source and the drain of the first transistor is electrically connected to a non-inverting input of a comparator through a first node. One of a source and a drain of a second transistor is electrically connected to a second terminal. The other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of a third transistor through a second node. The other of the source and the drain of the third transistor is electrically connected to a third terminal. A first capacitor is provided between the first node and the second node. An inverting input of the comparator is electrically connected to a fourth terminal. An output of the comparator is electrically connected to a fifth terminal.

Semiconductor device, battery pack, and electronic device

The invention of the application is the invention regarding a semiconductor device and a method for driving the semiconductor device. The semiconductor device includes first and second transistors, first to fifth switches, first to third capacitors, and a display element. The first transistor (M) comprises a back gate, a gate of the first transistor is electrically connected to the first switch (M), the second switch (M) and the first capacitor (C) are positioned between the gate of the first transistor and a source of the first transistor, the back gate of the first transistor is electrically connected to the third switch (M), the second capacitor (C) is positioned between the back gate of the first transistor and the source of the first transistor, the source of the first transistor is electrically connected to the fourth switch (M) and a drain of the second transistor (M), a gate of the second transistor is electrically connected to the fifth switch (M), the third capacitor (C) is positioned between the gate of the second transistor and a source of the second transistor, and the source of the second transistor is electrically connected to the display element ().

Semiconductor device and method for driving semiconductor device

A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of arithmetic blocks each including an arithmetic circuit portion and a memory circuit portion. The arithmetic circuit portion and the memory circuit portion are electrically connected to each other. The arithmetic circuit portion and the memory circuit portion have an overlap region. The arithmetic circuit portion includes, for example, a Si transistor, and the memory circuit portion includes, for example, an OS transistor. The arithmetic circuit portion has a function of performing product-sum operation. The memory circuit portion has a function of retaining weight data. A first driver circuit has a function of writing the weight data to the memory circuit portion. The weight data is written to all the memory circuit portions included in the same column with the use of the first driver circuit.

A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.

Semiconductor device comprising operation circuits and a switch circuit

A semiconductor device with a small circuit area and low power consumption is provided. The semiconductor device includes first to fourth cells, a current mirror circuit, and first to fourth wirings, and the first to fourth cells each include a first transistor, a second transistor, and a capacitor. In each of the first to fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. The first wiring is electrically connected to first terminals of the second transistors in the first cell and the second cell, the second wiring is electrically connected to first terminals of the second transistors in the third cell and the fourth cell, the third wiring is electrically connected to second terminals of the capacitors in the first cell and the third cell, and the fourth wiring is electrically connected to second terminals of the capacitors in the second cell and the fourth cell. The current mirror circuit is electrically connected to the first wiring and the second wiring.

A semiconductor device that has low power consumption and is capable of performing a product-sum operation is provided. The semiconductor device includes first and second cells, a first circuit, and first to third wirings. Each of the first and second cells includes a capacitor, and a first terminal of each of the capacitors is electrically connected to the third wiring. Each of the first and second cells has a function of feeding a current based on a potential held at a second terminal of the capacitor, to a corresponding one of the first and second wirings. The first circuit is electrically connected to the first and second wirings and stores currents I1 and I2 flowing through the first and second wirings. When the potential of the third wiring changes and accordingly the amount of current of the first wiring changes from I1 to I3 and the amount of current of the second wiring changes from I2 to I4, the first circuit generates a current with an amount I1−I2−I3+I4. Note that the potential of the third wiring is changed by firstly inputting a reference potential to the third wiring and then inputting a potential based on internal data or a potential based on information obtained by a sensor.

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Kanagawa, Japan

Munehiro Kozuma