Renesas Electronics Corporation

Nec Electronics Corporation

Muneaki Matsushige

Tetsuo Fukushi

Atsunori Hirobe

Hiroshi Furuta

Hiroyuki Takahashi

Junji Monden

Shouzou Uchida

Toshikatsu Jinbo

Kazutaka Kikuchi

Hiroyuki Satake

Hideyuki Nakamura

Toshiharu Okamoto

Susumu Takano

Toshifumi Takahashi

Kenichi Kuboyama

Toshihiko Funaki

Shuuichi Senou

A semiconductor device includes a memory mat having: a plurality of memory cells; a sense amplifier connected to a memory cell selected from the plurality of memory cells; a first power supply wiring; a first switch connected between the sense amplifier and the first power supply wiring and made an ON state in operating the sense amplifier; and a second switch connected to the sense amplifier and made an ON state in operating the sense amplifier, a second power supply wiring arranged outside the memory mat and connected to the first power supply wiring, a third power supply wiring arranged outside the memory mat and connected to the sense amplifier via the second switch, and a short switch arranged outside the memory mat and connected between the second and third power supply wirings. Here, in operating the sense amplifier, the short switch is made an ON state.

Semiconductor device having a high-speed memory with stable operation

Even when a driven circuit has a large-scale load, a small-scale step-down driver circuit can supply an internal potential to the driven circuit at high speed. A semiconductor integrated circuit device includes a step-down driver circuit which supplies, to a driven circuit to be driven by an internal potential lower than an external potential supplied from an external power supply, the internal potential. The step-down driver circuit includes an NMOS transistor having a drain coupled to an external power supply terminal to be coupled to the external power supply and a source to be coupled to a voltage supply point of the driven circuit and a driver circuit to drive the gate of the NMOS transistor.

Semiconductor integrated circuit device and semiconductor device

A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.

Semiconductor storage device

A semiconductor device includes a first semiconductor chip located over a substrate; and a second semiconductor chip located over the first semiconductor chip, wherein the first semiconductor chip includes a first internal power supply generation circuit that generates a first internal power supply voltage supplied to a first internal circuit; a first penetration electrode formed from an upper surface of the first semiconductor chip to an underside of the first semiconductor chip and electrically connected to the first internal power supply generation circuit; a first reference voltage generation circuit that generates a first reference voltage; and a second penetration electrode formed from the upper surface of the first semiconductor chip to the underside of the first semiconductor chip and electrically connected to the first reference voltage generation circuit.

Multilayered semiconductor device

An object of the invention is to make effective use of the structure of a multilayered semiconductor device that uses penetration electrodes in such a manner that the layered chips obtain stable internal power supply voltages with no increase in current consumption or in the area of the layered chips. Internal power supply generation circuits furnished in each of the layered core chips have their outputs commonly coupled via electrodes penetrating the layered core chips. This allows electrical charges to be shared among the core chips, optimizes internal power consumption of the multilayered semiconductor device as a whole, and inhibits fluctuations in the internal power supply voltages.

A semiconductor storage deviceaccording to an aspect includes a first memory areaand a second memory area. Memory cells MC_m_n and bit lines BL, BL_, . . . , BLmare disposed in a boundary areabetween the first and second memory areasand. The memory cells MC_m_n disposed in the boundary areaincludes memory cells into which no data is written, and a lineis formed in a place that overlaps memory cells disposed in the boundary areawhen the boundary areais viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.

A semiconductor storage deviceaccording to an aspect includes a first memory areaand a second memory area. Memory cells MC_m_n and bit lines BL, BL_, . . . . , BLm_are disposed in a boundary areabetween the first and second memory areasand. The memory cells MC_m_n disposed in the boundary areaincludes memory cells into which no data is written, and a lineis formed in a place that overlaps memory cells disposed in the boundary areawhen the boundary areais viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.

A semiconductor device including multiple subarrays arrayed in a matrix in the row and column directions, and respectively containing multiple memory cells, bit lines coupled to the memory cells, and precharge circuits (to charge the bit lines; column select signal lines extending in the column direction for selecting subarray columns; main word lines for selecting subarray rows; and precharge signal lines for supplying precharge signals to the precharge circuits; and at least two of the subarrays formed in the row direction or the column direction are controlled by the same logic according to the precharge signal.

Semiconductor device

A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.

Semiconductor apparatus

A semiconductor integrated circuit device includes a gate electrode of at least one of a P-channel MISFET (metal-insulator-semiconductor field-effect transistor) and an N-channel MISFET provided in a direction parallel to a direction of a well isolation boundary phase between the P-channel MISFET and the N-channel MISFET, a first diffusion layer having a same conductivity type as that of a drain diffusion layer of one of a plurality of ones of the MISFET provided in two regions with a drain diffusion layer of the MISFET therebetween through an isolation respectively in a direction orthogonal to the gate electrode, and a second diffusion layer having a conductivity type different from that of the drain diffusion layer of the one of the plurality of ones of the MISFET provided between the well isolation boundary phase and one of a source diffusion layer and the drain diffusion layer.

Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error

A MISFET includes a drain diffusion layer of a first conductivity type, a source diffusion layer of the first conductivity type, a gate electrode, and a substrate/well of a second conductivity type. In the MISFET, first diffusion layers of the first conductivity type are provided at two or more positions at predetermined intervals with an isolation therebetween respectively. The two or more positions are facing at least two sides of the element isolation insulation around the drain diffusion layer. A second diffusion layer of the second conductivity type is provided so as to be close to or to come in contact with the source diffusion layer.

A semiconductor integrated circuit device includes a first field-effect transistor and a second field-effect transistor, each of the first field-effect transistor and the second field-effect transistor having a gate electrode formed as a ring shape, a drain diffusion layer formed inside the gate electrode and a source diffusion layer formed outside the gate electrode and a substrate potential diffusion layer or a well potential diffusion layer disposed to contact each of the source diffusion layers of the first and the second field-effect transistors of the same conductivity type, the substrate potential diffusion layer or the well potential diffusion layer being formed with a semiconductor of a different conductivity type from the source diffusion layer. Different signals are input to each of the gate electrodes, the substrate potential diffusion layer or the well potential diffusion layer are formed between the source diffusion layer of the first field-effect transistor and the source diffusion layer of the second field-effect transistor.

Semiconductor integrated circuit device

A semiconductor integrated circuit includes a word line extending along a first direction, a first and a second N-well regions, a P-well region disposed between the first and the second N-well regions, a memory cell having a first, second, third, and fourth PMOS transistors, and a first and second NMOS transistors, the first and the second PMOS transistors disposed in the first N-well region along a second direction which is different from the first direction, the first and the second NMOS transistors disposed in the P-well region, and the third and the fourth PMOS transistors disposed in the second N-well region along the second direction.

Growing community of inventors

Kanagawa, Japan

Muneaki Matsushige