Kabushiki Kaisha Toshiba

Kioxia Corporation

Muneaki Maeno

Toshikazu Sei

Kenji Kimura

Toshiki Morimoto

Yukinori Uchino

Yutaka Tanaka

Hiroaki Suzuki

Akira Yamaguchi

Shinji Fujii

Yasunobu Umemoto

Kouichirou Inoue

Nobuhiko Kurata

A semiconductor integrated circuit includes a first power line to which a first voltage is continuously applied, a second power line, a power switch cell connected to the first power line and configured to output a second voltage to the second power line according to a first signal, a logic circuit driven by the second voltage applied via the second power line, a first circuit driven by the second voltage applied via the second power line and configured to output a third voltage to logic circuit according to a second signal which is an inverted signal of the first signal, and a second circuit driven by the second voltage applied via the second power line and configured to output a fourth voltage to logic circuit according to a third signal which is an inverted signal of the second signal, the fourth voltage being lower than the third voltage.

Semiconductor integrated circuit

A semiconductor integrated circuit comprises first and second transistors, and a resistive element. The first transistor includes first and second regions of first conductivity type in a first well region of opposite conductivity type, and a first gate electrode on the first well region between the first and second regions. The second transistor includes third and fourth region of second conductivity type in a second well region of opposite conductivity type, and a second gate electrode on the second well region between the third and fourth regions. The first region is connected to a first line, and the third and fourth regions are connected to a second line. The resistance element includes a first end connected to the first and second gate electrodes, a second end connected to the second line, and a resistive electrical path between the first and second ends including a portion of the third region.

According to one embodiment, a semiconductor integrated circuit comprises: a first flip-flop including a first input circuit, a first latch, a second latch, and a first output circuit; a second flip-flop including a second input circuit, a third latch, a fourth latch, and a second output circuit; and a clock buffer configured to output a common clock signal to the first flip-flop and the second flip-flop. A first output terminal of the second latch is coupled to an input terminal of the first output circuit, and a second output terminal of the second latch is directly coupled to an input terminal of the second input circuit.

A flip-flop circuit has a master latch circuit and a slave latch circuit. In the flip-flop circuit, the master latch circuit and the slave latch circuit share at least a pair of transistors. In response to the clock signal, the signal held in the master latch circuit can be output at higher speed as the output signal via the intermediate node, the slave latch circuit and the output circuit. The flip-flop circuit can be reduced in cell size and improved in processing speed.

Flip-flop circuit

A semiconductor device includes a flip-flop circuit formed in a CMOS semiconductor integrated circuit. The flip-flop circuit includes at least a first clock generating inverter that generates a first clock signal and a second clock generating inverter that generates a second clock signal obtained by inverting the first clock signal, the first clock generating inverter and the second clock generating inverter are arranged so as to sandwich a latch unit, the latch unit including a master latch unit and a slave latch unit in the flip-flop circuit, the first clock generating inverter and a first other circuit in the flip-flop circuit are configured to share a source region, the first other circuit being adjacent to the first clock generating inverter, and the second clock generating inverter and a second other circuit in the flip-flop circuit are configured to share a source region, the second other circuit being adjacent to the second clock generating inverter.

Semiconductor device

A third interconnection layer is disposed near a first interconnection layer and a second interconnection layer disposed above the first interconnection layer. The first interconnection layer and second interconnection layer are connected to each other by a regular via plug and a via plug for redundancy. The via plug for redundancy is disposed by the side of the regular via plug and between the regular via plug and the third interconnection layer. An extended portion of the second interconnection layer is extended from a portion connected to the via plug for redundancy on the second interconnection layer toward the third interconnection layer. The extended portion has a dimension smaller than the minimum dimension prescribed in the interconnection line design rule.

Semiconductor integrated circuit device comprising different level interconnection layers connected by conductor layers including conductor layer for redundancy

A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-contact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.

Computer-readable recording medium storing semiconductor designing program for improving both integration and connection of via-contact and metal

A basic cell placed in a semiconductor device comprises a via contact placed on a wiring grid having a pitch narrower than a pitch between a contact placed in a source region and a contact placed in a drain region of a transistor in a basic cell, and a wiring layer connected to the via contact, being used as a source terminal, a drain terminal, and a gate terminal of the transistor.

First and second IP cores are formed on one chip. Each of the first and second IP cores has metal layers. In the first IP core, an uppermost layer of the metal layers is thick and is a layer on which a core power source line is formed. In the second IP core, a metal layers equal in level to the uppermost layer in the first IP core becomes an intermediate layer. In the second IP core, thin intermediate layers are formed on this intermediate layer. Thin intermediate layers are layers on which signal lines are formed and have a narrow wiring pitch. In the second IP core, a layer on which a power source line is formed is provided on the thin intermediate layers.

A first cell block in which a plurality of standard cells with a large cell height are arranged and a second cell block in which a plurality of standard cells with a small cell height are arranged. In the second cell block, transistors are formed whose shape and characteristics are practically the same as those of the transistors provided in the standard cells with the large cell height arranged in the first cell block.

Standard-cell type semiconductor integrated circuit device with a mixed arrangement of standard cells differing in height

Semiconductor device, designing method thereof, and recording medium storing semiconductor designing program

A master slice layout technology is provided to improve integration density of a semiconductor integrated circuit such as ASIC. In particular, a plurality of gate basic cells are arranged on a semiconductor chip and then a wiring channel grid having non-uniform pitches is defined on the gate basic cells. If a layout of metal wirings is designed along the wiring channel grid, miniaturizable patterns can be set to smaller values while maintaining line widths of predetermined metal wirings such as power supply wirings at preselected values. Since flexibility for the layout of the metal wiring layers is large, miniaturization of the patterns can be attained even if design rules for basic cell process and wiring process are different.

Master slice LSI and layout method for the same

The present invention relates to the improvement in the degree of on-chip integration of memory cells utilizing a gate array layout. A plurality of three-transistor DRAM cells are disposed on a semiconductor chip implementing a regular cross-point array, each DRAM cell is made up of two nMOS transistors and one pMOS transistor formed in one basic cell. The semiconductor chip disposes therein nMOS memory-cell blocks and pMOS memory-cell blocks alternately, effectively utilizing the gate array layout.

Growing community of inventors

Yokohama, Japan

Muneaki Maeno