Abb Technology Ag

Abb Schweiz Ag

Mqsemi Ag

Abb Power Grids Switzerland Ag

Hitachi Energy Ltd

Abb Research Ltd.

Abb Technology Ltd

Hitachi Energy Switzerland Ag

Munaf Rahimo

Arnost Kopta

Iulian Nistor

Jan Vobecky

Chiara Corvasce

Maxi Andenna

Umamaheswara Vemulapati

Renato Minamisawa

Liutauras Storasta

Martin Arnold

Lars Knoll

Andrei Mihaila

Wolfgang Janisch

Florin Udrea

Ulrich Schlapbach

Christoph Von Arx

Peter Karl Steimer

Pietro Cairoli

Stefan Linder

Chunlei Liu

Luca De-Michielis

Matthias Bator

Bruno Agostini

Francesco Agostini

Daniele Torresin

Mathieu Habert

Falah Hosini

Slavo Kicin

Marco Bellini

Peter Streit

Jürgen Schuderer

Raffael Schnell

Holger Bartolf

Franc Dugal

Charalampos Papadopoulos

Marina Antoniou

Hamit Duran

Lukas Hofstetter

Eustachio Faggiano

Juergen Schuderer

Friedhelm Bauer

Franziska Brem

Thomas Stiasny

Neophytos Lophitis

Nicola Schulz

Ricardo Bini

Riccardo Bini

Manuel Le Gallo

Madhan Mohan

Siva Nagi Reddy Pamulapati

Manuel Le-Gallo

Neophythos Lophitis

Lulian Nistor

Thomas Clausen

Babak H-Alikhani

Frank Ritchie

Kati Hemmann

Elizabeth Buitrago

Uwe Badstuebner

Christian Spindler

An insulated gate bipolar transistor includes a source electrode, a collector electrode, a source layer, a base layer, a drift layer and a collector layer. Trench gate electrodes extend through the base layer into the drift layer. A channel is located between the source layer, the base layer and the drift layer. A trench Schottky electrode is adjacent to one of the trench gate electrodes and includes an electrically conductive Schottky layer arranged lateral to the base layer and extends through the base layer into the drift layer. The Schottky layer is electrically connected to the source electrode. Collection areas are located in the drift layer at a respective trench gate electrode bottom of the trench gate electrodes or of the trench Schottky electrode. The Schottky layer forms a Schottky contact to the collection area at a contact area.

Insulated gate bipolar transistor including trench Schottky electrode

A Metal Oxide Semiconductor (MOS) cell design has traditional planar cells extending in a first dimension, and trenches with their length extending in a third dimension, orthogonal to the first dimension in a top view. The manufacturing process includes forming a horizontal channel, and a plurality of trenches discontinued in the planar cell regions. Horizontal planar channels are formed in the mesa of the orthogonal trenches. A series connected horizontal planar channel and a vertical trench channel are formed along the trench regions surrounded by the first base. The lack of a traditional vertical channel is important to avoid significant reliability issues (shifts in threshold voltage Vth). The planar cell design offers a range of advantages both in terms of performance and processability. Manufacture of the planar cell is based on a self-aligned process with minimum number of masks, with the potential of applying additional layers or structures.

Semiconductor device and method for producing same

A semiconductor device with an active transistor cell comprising a p-type first and second base layers, surrounding an n-type source region, the device further comprising a plurality of first gate electrodes embedded in trench recesses, has additional gate runners formed adjacent to the first base layer, outside the active cell, and contacting the first gate electrodes at the cross points thereof. The additional gate runners do not affect the active cell design in terms of cell pitch i.e., the design rules for cell spacing, hole drainage between the cells, or gate-collector capacitance, hence resulting in optimum low conduction and switching losses. The transistor cell and layout designs offer a range of advantages both in terms of performance and manufacturability, with the potential of applying additional layers or structures.

Semiconductor device layouts

In this patent application, a new Metal Oxide Semiconductor MOS planar cell design concept is proposed. The inventive power semiconductor includes a planar cell forming a horizontal channel and a plurality of trenches, which are arranged orthogonally to the plane of the planar cells. A second p base layer is introduced which extends perpendicularly deeper than the source region and laterally to the same distance/extent as the source region. Therefore, a vertical channel is prevented from forming in the trench regions while allowing the horizontal channels to form. This is extremely important in order to avoid significant issues (i.e. shifts in Vth) encountered in prior art IGBT designs. The new cell concept adopts planar MOS channel and Trench technology in a single MOS cell structure. The new design offers a wide range of advantages both in terms of performance (reduced losses, improved controllability and reliability), and processability (narrow mesa design rules, reliable planar process compatibility) and can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials such as Silicon Carbide SiC. Furthermore, the device is easy to manufacture, because the inventive design can be manufactured based on a self-aligned process with minimum number of masks, with the potential of additionally applying enhancement layers and/or reverse conducting type of structures.

A semiconductor device with an active transistor cell comprising a p-doped first and second base layers, surrounding an n type source region, the device further comprising a plurality of first gate electrodes embedded in trench recesses, has additional fortifying p-doped layers embedding the opposite ends of the trench recesses. The additional fortifying layers do not affect the active cell design in terms of cell pitch i.e., the design rules for transistor cell spacing, or hole drainage between the transistor cells, but reduce the gate-collector parasitic capacitance of the semiconductor, hence leading to optimum low conduction and switching losses. To further reduce the gate-collector capacitance, the trench recesses embedding the first gate electrodes can be formed with thicker insulating layers in regions that do not abut the first base layers, so as not to negatively impact the value of the threshold voltage.

Semiconductor device and method for designing thereof

A reverse conducting insulated gate power semiconductor device is provided which comprises a plurality of active unit cells () and a pilot diode unit cell () comprising a second conductivity type anode region () in direct contact with a first main electrode () and extending from a first main side () to a first depth (d). Each active unit cell () comprises a first conductivity type first source layer () in direct contact with the first main electrode (), a second conductivity type base layer () and a first gate electrode (), which is separated from the first source layer () and the second conductivity type base layer () by a first gate insulating layer () to form a first field effect transistor structure. A lateral size (w) of the anode region () in an orthogonal projection onto a vertical plane perpendicular to the first main side () is equal to or less than 1 μm. On a first lateral side surface of the anode region () a first insulating layer () is arranged and on an opposing second lateral side surface of the anode region () a second insulating layer () is arranged. And a distance between the first insulating layer () and the second insulating layer () is equal to or less than 1 μm, the first insulating layer () extending vertically from the first main side () to a second depth (d), and the second insulating layer () extending vertically from the first main side () to a third depth (d), wherein the first depth (d) is less than the second depth (d) and less than the third depth (d).

Reverse conducting insulated gate power semiconductor device having low conduction losses

A MOS cell based on a simple and self-aligned process is provides a planar cell forming a horizontal MOS channel, and a plurality of trench regions, which are arranged at an angle with respect to the longitudinal direction of the planar cells. The new cell concept can adopt both planar MOS channels and Trench MOS channels in a single MOS cell structure, or planar MOS channels alone, while utilising the trenches to improve the current spreading of the planar MOS channels. Floating P-doped regions at the bottom of the trench regions protect the device against high peak electric fields. The orthogonal trench recesses are discontinued in their longitudinal direction to allow the planar channels to conduct electrons. The design can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials.

Fortified trench planar MOS power transistor

A thin non-punch-through semiconductor device with a patterned collector layer on the collector side is proposed. The thin NPT RC-IGBT semiconductor device has a collector layer with a pattern of p/n shorts, an emitter side structured as a functional MOS cell, a base layer arranged between the emitter and the collector sides, but without the use of a buffer/field-stop layer. A low doped bipolar gain control layer having a thickness of less than 10 &#x3bc;m may be used in combination with a short pattern of the collector to reduce the bipolar gain and achieve thinner devices with lower losses and high operating temperature capability. The doping concentration of the base layer and a thickness of the base layer are adapted such that the distance from the end of the electric field region to the patterned collector, at breakdown voltage, is less than 15% of the total device thickness.

Non-punch-through reverse-conducting power semiconductor device and method for producing same

Power transistors relying on planar MOS cell designs suffer from the 'hole drainage effect'; addition of an enhancement layer creates significant loss of breakdown voltage capability. The Fortified Enhanced Planar MOS cell design provides an alternative that uses enhancement layers, field oxides, and gate trenches without suffering from the loss of blocking voltage. A low doped P-type 'fortifying layer' reduces the high peak electric fields that develop in blocking mode in critical regions. The fortifying layer can be electrically biased through an additional electrical contact, which can be arranged at die level, not at transistor cell level. Due to the low dopant concentration of the fortifying layer, no additional MOS channels need to be formed, and the electrons will flow thru the non-inverted regions of the fortifying layer. The new design shows advantages in performance, ease of processing, and applicability.

Semiconductor device with fortifying layer

A power transistor layout structure is described that includes a planar cell with a planar gate electrode forming an horizontal MOS channel, and a plurality of trench recesses with gate electrodes, which are arranged at various angles to the longitudinal direction of the planar cells. This cell concept can adopt both planar MOS channels, and Trench MOS channels in a single MOS cell structure. As an alternative, the planar cell gate electrode may be grounded. The device is easy to manufacture based on a self-aligned process with minimum number of masks, with the potential of applying additional layers.

Trench planar MOS cell for transistors

A bipolar semiconductor device includes at least a four-layer structure, a first main side with a first electrical contact, and a second main side with a second electrical contact separated from the first main side by at least a base layer of first conductivity type. A shorting layer of the first conductivity type is arranged on the second main side of the base layer. A third layer includes a patterned highly conductive material, such as metal and/or silicides, graphene, etc., and is deposited on the shorting. A fourth layer of the second conductivity type is arranged directly on the third layer, inserted between the shorting layer and the second electrical contact. This concept can be applied to any non-punch-through or punch-through reverse conducting IGBT designs, but is particularly effective for devices using thin wafers, and is also applicable to bipolar diodes in order to improve a soft recovery process.

Bipolar semiconductor device and method for manufacturing such a semiconductor device

A Metal Oxide Semiconductor (MOS) trench cell includes a plurality of main gate trenches etched in the semiconductor body. In conduction state, the main gate electrode forms vertical MOS channels on the short edges and at least on a portion of the long edges in a mesa of the semiconductor body between neighbouring trenches. The longitudinal direction of the main gate trenches is oriented at an angle between 45 degrees to 90 degrees compared to the longitudinal direction of the first main electrode contacts, in a top plane view. This design offers a wide range of advantages both in terms of performance (reduced losses, improved controllability and reliability) and processability (narrow mesa design rules) and can be applied to both IGBTs and MOSFETs based on silicon or wide bandgap materials such as silicon carbide SiC, zinc oxide (ZnO), gallium oxide (Ga2O3), gallium nitride (GaN), diamond.

Semiconductor device having a gate electrode formed in a trench structure

An insulated gate power semiconductor device (), comprises in an order from a first main side () towards a second main side () opposite to the first main side () a first conductivity type source layer (), a second conductivity type base layer (), a first conductivity type enhancement layer () and a first conductivity type drift layer (). The insulated gate power semiconductor device () further comprises two neighbouring trench gate electrodes () to form a vertical MOS cell sandwiched between the two neighbouring trench gate electrodes (). At least a portion of a second conductivity type protection layer () is arranged in an area between the two neighbouring trench gate electrodes (), wherein the protection layer () is separated from the gate insulating layer () by a first conductivity type channel layer () extending along the gate insulating layer ().

Insulated gate power semiconductor device and method for manufacturing such device

A bidirectional thyristor device includes a semiconductor wafer with a number of layers forming pn junctions. A first main electrode and a first gate electrode are arranged on a first main side of the wafer. A second main electrode and a second gate electrode are arranged on a second main side of the wafer. First emitter shorts penetrate through a first semiconductor layer and second emitter shorts penetrate through a fifth semiconductor layer. In an orthogonal projection onto a plane parallel to the first main side, a first area occupied by the first semiconductor layer and the first emitter shorts overlaps in an overlapping area with a second area occupied by the fifth semiconductor layer and the second emitter shorts. The overlapping area, in which the first area overlaps with the second area, encompasses at least 50% of a total wafer area occupied by the semiconductor wafer.

Bidirectional phase controlled thyristor (BiPCT)&#x2014;a new semiconductor device concept

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Munaf Rahimo