Electronics and Telecommunications Research Institute

Mun Yang Park

Hyun Kyu Yu

Jong Dae Kim

Cheon Soo Kim

Seong Do Kim

Young Ho Kim

Seon-Ho Han

Chong Ki Kwon

Pil Jae Park

Gyu Hyung Cho

Jong Kee Kwon

Ja Yol Lee

Seong-Do Kim

Won Chul Song

Yong-Sik Youn

Beaung Woo Lee

Bon Tae Koo

Min-Hyung Cho

Jin Ho Han

Gyu Hyeong Cho

Jae Hoon Shim

Sang-Gug Lee

Ik Soo Eo

Young-deuk Jeon

Jang Hong Choi

Jin Gun Koo

Min Hyung Cho

Song Cheol Hong

Hee Bum Jung

Seung Chul Lee

Young-Jun Kim

Seon Ho Han

Sang-Kyun Kim

Nam-soo Kim

Byung-Do Yang

Hyun Ho Boo

YoungSeok Baek

Myung Shin Kwak

Sun Bo Shim

Ki Su Kim

Q Sang Song

Ki-Hyuk Sung

Lee-Sup Kim

The inventive concept relates to a body composition analysis system. A body composition analysis system according to an embodiment of the inventive concept includes a sinusoidal signal generator, a synchronous detector, and a bioimpedance analyzer. The sinusoidal signal generator converts a digital sinusoidal signal having a target frequency into an analog sinusoidal signal. The synchronous detector extracts a target frequency component of a bioelectrical signal generated in response to an analog sinusoidal signal based on the digital sinusoidal signal. The bioimpedance analyzer calculates the bioimpedance based on the target frequency component of the bioelectrical signal. According to the inventive concept, it is possible to improve the selectivity for extracting the target frequency component of the bioelectrical signal and to reduce the area and variations of characteristics for the implementation of the integrated circuit.

Body composition analysis system

Disclosed are a pulse radar apparatus and an operating method of the pulse radar apparatus, the pulse radar apparatus including a transmitter configured to receive a reference signal as a transmission clock signal, and transmit a transmission pulse to an object based on the transmission clock signal, a negative feedback loop configured to delay the reference signal and output the delayed reference signal as a reception clock signal, and a receiver configured to restore, based on the reception clock signal, a reflection pulse received in response to the transmission pulse being reflected from the object, wherein the negative feedback loop is configured to generate a delay control signal using the reference signal and a predetermined waveform signal generated by a waveform generator, delay the reference signal based on the delay control signal, and adjust the delay control signal by controlling the waveform generator to change the predetermined waveform signal.

Pulse radar apparatus and operating method of pulse radar apparatus

A digital RF receiver does not use a separate receiver according to a mode and a band for multi-mode reception, MIMO reception, and bandwidth extension reception, and changes only setting variables in a single receiver structure so as to implement multi-mode reception, MIMO reception, bandwidth extension reception, and/or simultaneous multi-mode operation, such that complexity of the receiver, development cost, and power consumption can be reduced.

Digital radio frequency (RF) receiver

A digital RF converter, a digital RF modulator, and a transmitter are provided. The digital RF converter includes a delta-sigma modulated bits (DSMB) sub-block that generates a current magnitude corresponding to least-significant n bits among input signals at a first sampling speed, a least-significant bit (LSB) sub-block that generates a current magnitude corresponding to intermediate k bits among the input signals at a second sampling speed lower than the first sampling speed, and a most-significant bit (MSB) sub block that generates a current magnitude corresponding to most-significant m bits among the inputs signals at the second sampling speed.

Digital RF converter, digital RF modulator and transmitter including the same

There is provided an apparatus and method for In-phase/Quadrature-phase (I/Q) mismatch calibration. The apparatus includes: a symmetrical point extracting part receiving continuous wave signals and extracting an I/Q channel average locus of the continuous wave signals; an error extracting part extracting a degree of distortion of the continuous wave signals from the extracted I/Q channel average locus; and a calibrating part calibrating a mismatch between I-channel signals and Q-channel signals of the continuous wave signals using the degree of distortion of the continuous wave signals.

Apparatus and method for I/Q mismatch calibration

There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result.

Frequency synthesizer including a digital lock detector

Digital lock detector and frequency synthesizer using the same

A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.

Multi-metal coplanar waveguide

Provided are a voltage controlled digital analog oscillator and a frequency synthesizer using the same, the oscillator comprising an oscillator having a frequency of an output signal being determined by a voltage inputted to an analog input end and a digital value inputted to a digital input end; and a digital tuner for comparing the voltage inputted to the analog input end to first and second threshold voltages and changing the digital value inputted to the digital input end according to the result, whereby it is possible to obtain a broadband frequency output with less noise.

Voltage controlled digital analog oscillator and frequency synthesizer using the same

An analog variable gain amplifier (VGA) adjusting a signal level of a mobile communication system is provided. More particularly, design of a VGA using an operational transconductance amplifier (OTA) having a wide linear input/output range is disclosed. The VGA includes two double-differential-pair OTAs and feedback resistors. A first differential input of a first double differential pair OTA receives an input signal from the forward stage, and a second differential input is negatively fed back through a differential output and a passive resistor. An input in which a first block of the connection structure and first and second differential inputs of a second double differential pair OTA are connected receives an output signal of the first block stage. The output is negatively fed back in series through a variable resistor whose resistance varies exponentially with an adjustment voltage from outside. According to the VGA, it is possible to provide a characteristic of linear variation of gain on a logarithmic scale with respect to a control voltage with a simple and inexpensive constitution. In addition, the VGA can be designed for a low pass filter having a conventional OTA used for a core circuit, and has a simple circuit structure. Therefore, the VGA is convenient for high integration and low-power design, and thus is appropriate for a terminal chip and so forth.

Variable gain amplifier and variable gain amplifier module

Provided is a method of acquiring a high linear characteristic and a low distortion in a transconductor (operational transconductance amplifier), especially, in a triode region type transconductor among CMOS transconductors. A resistance is inserted in a source or a drain of an input triode transistor. The transconductor has a simple circuit structure, and has a large linear region, constant transconductance and low total harmonic distortion (THD) characteristic within an error region.

Method of acquiring low distortion and high linear characteristic in triode-typed transconductor

Disclosed is a CMOS variable gain amplifier (VGA). The variable gain amplifier comprises a voltage-current converter for converting voltages of a wide input range into currents, a current shared circuit for receiving the currents from the voltage-current converter and controlling values of output currents depending on first and second control voltages, and a current-voltage converter for converting the output currents from the current shared circuit into differential voltages depending on a bias voltage in order to obtain a variable gain. The voltage amplifier having a variable gain is provided by controlling the value of the output current of the drain terminal against the gate voltage of the NMOS transistor constituting the current shared circuit. Therefore, an integrated circuit (IC) type variable gain amplifier operating a high speed at a low supply voltage can be obtained.

Variable gain amplifier

Provided is an active load circuit of a voltage gain amplifier, which allows a high voltage gain with a low supply voltage operation in high-frequency range. The active load circuit includes a PMOS transistor which is connected between the amplifying unit and a power supply voltage and functions as a load element in a low frequency range; a negative feedback buffering unit which is connected to the gate of the PMOS transistor and functions as a common drain amplifier to stabilize the output voltage of the voltage gain amplifier and drive the voltage gain amplifier at a low voltage; and a capacitor which is connected to the negative feedback buffering unit and compensates for both an impedance and a frequency characteristics when the voltage gain amplifier operates in a high frequency range.

Active load circuit for low-voltage CMOS voltage gain amplifier with wide bandwidth and high gain characteristic

Provided is a transconductor capable of eliminating a direct current (DC) offset component of a signal and compensating a mismatch of the signal. The transconductor includes amplifiers of simple circuit structures, and a common mode control DC offset elimination circuit. The transconductor includes a common mode control DC offset elimination circuit unit receiving input/output voltages to stabilize the current supplying and the output DC value, a first amplifier and a second amplifier reducing a mismatch in a transconductor circuit and increasing an output resistance, in order to prevent a signal distortion or a wrong operation of the circuit that is caused by the mismatch signal and unstable DC voltage.

Operational transconductance amplifier with DC offset elimination and low mismatch

Provided is a CMOS exponential function generating circuit capable of compensating for the exponential function characteristic according to temperature variations. The exponential function generating circuit includes an voltage scaler scaling the value of an external gain control voltage signal, an exponential function generating unit generating exponential function current and voltage in response to a signal output from the voltage scaler, a reference voltage generator providing a reference voltage to the exponential function generating unit, and a temperature compensator compensating for the exponential function characteristic according to temperature variations.

CMOS exponential function generating circuit with temperature compensation technique

Growing community of inventors

Daejeon, South Korea

Mun Yang Park