Hyundai Electronics Industries Co. Ltd.

Mun Weon Ahn

Hoai Sig Kang

Jong Hong Bae

Han Heung Kim

An analog-to-digital converter is provided. The analog-to-digital converter capable of increasing the processing speed of the converter by using a number of SAR registers. The analog-to-digital converter, includes: a storage circuit for storing a first, a second and a third digital signals, respectively; a controller for controlling conversions of two bits contained in one of the digital signals stored at the storing means in response to a first, a second and a third comparing signals; a circuit, having a first, a second and a third digital-to-analog converters, for converting the first, the second and the third digital signals by using each of the digital-to-analog converters to provide a first, a second and a third analog reference signals; and a comparator for comparing each of the analog reference signals to an analog input signal which is to be converted, to provide said first, said second and said third comparing signals, and having a first, a second and a third comparators each of which performs each of the comparisons.

Apparatus and a method for analog to digital conversion using plural reference signals and comparators

In a high performance microprocessor adopting a superscalar technique, necessarily using a cache memory, TLB, BTB and etc. and being implemented by 4-way set associative, there is provided an LRU memory capable of performing a pseudo replacement policy and supporting multi-port required for operating various blocks included in the microprocessor. The LRU memory comprises an address decoding block for decoding an INDEX.sub.-- ADDRESS to produce a READ.sub.-- WORD and a WRITE.sub.-- WORD in response to the first phase and a second phase of the CLOCK signal, respectively; an LRU storing block; a way hit decoding block for decoding a WAY.sub.-- HIT to produce a MODIFY CONTROL signal in response to the second phase of the CLOCK signal; a data modifying block for latching a READ.sub.-- DATA from the LRU storing block to produce a DETECTED DATA and modifying it in response to the MODIFY CONTROL signal so as to produce a WRITE.sub.-- DATA to the LRU storing block; and a write way decoding block for analyzing the DETECTED DATA so as to produce a WRITE.sub.-- WAY. This LRU memory reduces the load of superscalar microprocessor required for controlling the cache memory, TLB and BTB and simplifies an interface therebetween, so as to perform the LRU updating process in high speed, thereby improving the performance of the superscalar microprocessor.

High-performance LRU memory capable of supporting multiple ports

An apparatus serves to map internal registers into I/O addresses to select an internal register and perform read and write operations in the I/O address space of the PCMCIA host adapter, using the index mapping mechanism. The apparatus according to the present invention includes a plurality of internal registers for storing an input data, being arranged in the PCMCIA card; a plurality of first AND gates for producing a first control signal in response to index signals from an index register; a plurality of second AND gates for producing a register enabling signal in response to the first control signal and a data write signal from CPU; and a plurality of AND gates means for producing a third control signal outputting data stored in the internal register.

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Kyoungki-do, South Korea

Mun Weon Ahn