Skhynix Inc.

Mun Seon Jang

Saeng Hwan Kim

Jin Ho Jeong

Dae Suk Kim

Chang Ki Baek

Sang Uhn Cha

In Tae Kim

Dong Hee Han

Tae Kyun Kim

Hoiju Chung

Kyung Whan Kim

Jae Woong Yun

A Ram Rim

Sang Woo Yoon

Seong Yoon Kang

Byoung Chul Lee

An electronic system includes a controller configured to output a command, external row addresses, and external column addresses, receive a flag signal, and output the flag signal to a host. The electronic system also includes a semiconductor device configured to correct an error of internal data output from a memory cell selected based on the command, the external row addresses, and the external column addresses to output error-corrected internal data as data, and output the flag signal that is enabled when correcting the error in the internal data a set number of times.

Electronic system for monitoring error of address

A memory includes a memory core, an error correction code (ECC) engine, and an error determination circuit. The ECC engine is configured to generate an error correction code to be stored in the memory core together with write data by using the write data during an encoding operation, and to correct an error of read data read from the memory core using the error correction code read from the memory core during a decoding operation. The error determination circuit is configured to determine that, during the decoding operation, a 1-bit error exists when upper index portions of syndromes generated by the ECC engine have odd weights, and to determine that a correctable 2-bit error exists when the upper index portions of the syndromes are one of predetermined even weight patterns.

Memory including error correction code engine

A memory device includes a memory cell area including a plurality of cell blocks divided into a plurality of normal cell blocks, at least one ECC cell block, and at least one redundancy cell block, the plurality of cell blocks being configured to output data and error correction codes; an error correction circuit configured to generate error-corrected data by correcting errors in the data using the error correction codes; a first switch group configured to output the error-corrected data while performing, according to first repair control information, a shifting operation on the error-corrected data; and a second switch group configured to transfer the data from the memory cell area to the error correction circuit while performing, according to second repair control information, a zero-padding operation on the data output from one of the cell blocks.

Memory device including error correction device

A memory system may include a memory core; and an ECC engine configured to, during a write operation, perform a logical operation on an M-bit write data and an H matrix, and generate an N-bit first error correction code and an N-bit second error correction code to be stored in the memory core together with the write data, where N is an integer of 2 or more and M is a multiple of N. The H matrix may include an upper matrix having a size of N*(M+2N) and a lower matrix having a size of N*(M+2N), the lower matrix may include M/N Tcompanion matrices each having a size of N*N, and k of the Tcompanion matrices may have values which are positive integers different by N or more for each companion matrix.

Memory system including ECC engine

A semiconductor module includes an address control circuit configured to generate an internal address based on an address in a first read operation and a second read operation that are sequentially performed and configured to generate multiple decoding enable signals and an error information enable signal, a memory circuit including multiple mats and configured to output internal data based on the internal address and the multiple decoding enable signals in the first read operation and configured to output internal meta data and second internal parities based on the internal address and the multiple decoding enable signals in the second read operation, and an error information storage circuit configured to output first internal parities based on the internal address and the error information enable signal in the first read operation.

Semiconductor module for performing error correction operation

A memory device includes a plurality of first cell blocks configured to store first data; a second cell block configured to store second data; a third cell block configured to store third data; a repair information storage circuit configured to output, based on repair information stored therein, a repair use signal corresponding to an input address; and an error correction circuit configured to: receive the second data as a first error correction code from the second cell block while selectively receiving, according to the repair use signal, the third data as a second error correction code from the third cell block, and correct errors in the first data from the first cell blocks using the first and second error correction codes.

A memory system includes a memory controller including: a memory core configured to store data and an error correction code corresponding to the data; a syndrome generator configured to generate a first syndrome by substituting the data and the error correction code, read from the memory core, into a first check matrix, and generate a second syndrome by substituting the data and the error correction code, read from the memory core, into a second check matrix; and an error correction unit configured to correct an error of the read data and error correction code by using the first syndrome and the second syndrome, wherein constituents having values of '1' in the first check matrix have values of '1' also in the second check matrix.

Memory system and operating method thereof

A semiconductor device may include a data storage region, a parity storage region and an error correction circuit. The data storage region may be configured to store first data and second data. The parity storage region may be configured to store a parity. The error correction circuit may be configured to correct an error of the first data or an error of the second data and the parity, based on a transmission selection signal.

Semiconductor devices

A semiconductor device may include an inversion control signal generation circuit, a pattern control signal generation circuit, and a data input/output (I/O) circuit. The inversion control signal generation circuit may generate an inversion control signal according to a logic level combination of bit patterns included in at least one of a first address and a second address. The pattern control signal generation circuit may generate a pattern control signal from a pre-control signal in response to the inversion control signal. In response to the pattern control signal, the data input/output (I/O) circuit may generate data signals that will be output to an internal I/O line based on data signals loaded on a local I/O line.

A semiconductor device may include a syndrome generation circuit and a failure detection circuit. The syndrome generation circuit may generate a syndrome signal corresponding to a pattern of an output data signal. The failure detection circuit may detect the syndrome signal and sequentially store the syndrome signal to generate a first syndrome signal and a second syndrome signal if an error is detected from the syndrome signal. The failure detection circuit may generate a failure detection signal which is enabled if a logic level combination of the first syndrome signal is different from a logic level combination of the second syndrome signal.

A power-up circuit of a semiconductor apparatus includes a detection block configured to detect a first target level of an external voltage and activate a power-up signal; and a bias block configured to divide the external voltage according to a division ratio that is variable in response to the power-up signal, and output a bias voltage.

Semiconductor apparatus

An amplification circuit of a semiconductor apparatus includes a first amplification unit configured to amplify a difference between an input voltage and a reference voltage and generate a preliminary amplification signal, a second amplification unit configured to secondarily amplify the preliminary amplification signal and generate an amplification signal, and a compensation unit configured to form an addition current path.

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Seoul, South Korea

Mun Seon Jang